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MT9072AB Datasheet(PDF) 179 Page - Zarlink Semiconductor Inc

Part # MT9072AB
Description  Octal T1/E1/J1 Framer
PDF  275 Pages
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

MT9072AB Datasheet(HTML) 179 Page - Zarlink Semiconductor Inc

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MT9072
Data Sheet
179
Zarlink Semiconductor Inc.
Bit
Name
Functional Description
15
#
not used.
14
13
12
11
10
31C4
31C3
31C2
31C1
31C0
(11111)
Timeslot 31 CST Map Bits. The selection of these bits results in a mapping of the transmit
PCM30 timeslot 31, from a specific CSTi timeslot; and similarly, maps receive PCM30 timeslot
31, to a specific CSTo timeslot. PCM30 timeslot 31 data is mapped to/from CST channel n
(n=0 to 31), where n is the BCD (Binary Coded Decimal) equivalent of 31C4 to 31C0 with 31C4
being the most significant bit.
Bit Settings
Selected
31C4
31C3
31C2
31C1
31C0
CST Timeslot
0000
0
0
0000
1
1
0
001
0
2
etc.
1111
1
31
CCS (CSIG=1 of register address Y03) and CST (TS31E=1 of register address Y06) must be
selected for these operations to be valid.
9
8
7
6
5
16C4
16C3
16C2
16C1
16C0
(10000)
Timeslot 16 CST Map Bits. The selection of these bits results in a mapping of the transmit
PCM30 timeslot 16, from a specific CSTi timeslot; and similarly, maps receive PCM30 timeslot
16, to a specific CSTo timeslot. PCM30 timeslot 16 data is mapped to/from CST channel n
(n=0 to 31), where n is the BCD equivalent of 16C4 to 16C0 with 16C4 being the most
significant bit.
Bit Settings
Selected
16C4
16C3
16C2
16C1
16C0
CST Timeslot
0000
0
0
0000
1
1
0
001
0
2
etc.
1111
1
31
CCS (CSIG=1 of register address Y03) and CST (TS16E=1 of register address Y06) must be
selected for these operations to be valid.
4
3
2
1
0
15C4
15C3
15C2
15C1
15C0
(01111)
Timeslot 15 CST Map Bits. The selection of these bits results in a mapping of the transmit
PCM30 timeslot 15, from a specific CSTi timeslot; and similarly, maps receive PCM30 timeslot
15, to a specific CSTo timeslot. PCM30 timeslot 15 data is mapped to/from CST channel n
(n=0 to 31), where n is the BCD equivalent of 15C4 to 15C0 with 15C4 being the most
significant bit.
Bit Settings
Selected
15C4
15C3
15C2
15C1
15C0
CST Timeslot
0000
0
0
0000
1
1
0
001
0
2
etc.
1111
1
31
CCS (CSIG=1 of register address Y03) and CST (TS15E=1 of register address Y06) must be
selected for these operations to be valid.
Table 149 - CCS to ST-BUS CSTi and CSTo Map Control Register (R/W Address Y07) (E1)



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