DSP56156ROM datasheet(40/76 Pages) MOTOROLA

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AC Electrical Characteristics and Timing

DSP56156 Data Sheet

MOTOROLA

NOTES:

1. “Host Synchronization Delay (tHSDL)” is the time period required for the DSP56156 to sample any

external asynchronous input signal, determine whether it is high or low, and synchronize it to the

internal clock.

2. See Host Port Considerations.

3. HREQ is pulled up by 1 k

Ω.

4. Only if two consecutive reads from one of these registers are executed.

Table 19 Host Port Timing (continued)

Num

Characteristic

40 MHz

50 MHz

60 MHz

Unit

Min

Max

Min

Max

Min

Max

110

HR/W Low Setup Time before HEN Assertion

—

111

HR/W Low Hold Time after HEN Deassertion

—

112

HR/W High Setup Time to HEN Assertion

—

113

HR/W High Hold Time after HEN/HACK

Deassertion

—

4—3—

114

HA0-HA2 Setup Time before HEN Assertion

—

7.5

—

115

HA0-HA2 Hold Time after HEN Deassertion

—7—6—

116

DMA HACK Assertion to HREQ Deassertion

(See Note 3)

52T

+37

52T

+36

42T

+35

117

DMA HACK Deassertion to HREQ

Assertion (See Note 3)

for DMA RXL Read

for DMA TXL Write

for All Other Cases

tHSDL

+3T+5

tHSDL

+2T+5

—

tHSDL

3T+5

tHSDL

+2T+5

—

tHSDL

+3T+4

tHSDL

+2T+4

—

118

Delay from HEN Deassertion to HREQ

Assertion for RXL Read (See Note 3)

tHSDL

+3T+5

—tHSDL

+3T+5

—tHSDL

+3T+4

—ns

119

Delay from HEN Deassertion to HREQ

Assertion for TXL Write (See Note 3)

tHSDL

+2T+5

—tHSDL

+2T+5

—tHSDL

+2T+4

—ns

120

Delay from HEN Assertion to HREQ

Deassertion for RXL Read, TXL Write

(See Note 3)

52T

+37

52T

+36

52T

+35

Host Port Timing

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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