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DSP56156ROM Datasheet(PDF) 66 Page - Motorola, Inc |
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DSP56156ROM Datasheet(HTML) 66 Page - Motorola, Inc |
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66 / 76 page ![]() Design Considerations MOTOROLA DSP56156 Data Sheet 61 capacitor lead. The use of at least a four lay- er board is recommended, employing two inner layers as VCC and GND planes. All output pins on this DSP have fast rise and fall times. Printed Circuit Board (PCB) trace length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data buses as well as the PS/DS, BS, RD, WR, R/W, inter- rupt, and HEN pins. Maximum PCB trace lengths on the order of 6" are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitanc- es due to PCB traces. Attention to proper PCB layout and bypassing becomes espe- cially critical in systems with higher capac- itive loads because these loads create higher transient currents in the VCC and GND circuits. Clock signals should not be run across many signals and should be kept away from analog power and ground traces as well as any analog signals. See Figure 44 for more details. Power, Ground, and Noise Table 26 Power and Ground Connections Circuitry Power Ground Signal Name Pin # Signal Name Pin # Address Bus Buffers VCC1 VCC2 92 103 GND0 GND1 GND2 GND3 89 95 101 108 Data Bus Buffers VCC3 VCC4 4 15 GND4 GND5 GND6 GND7 1 7 12 18 Bus Control Buffers VCC5 36 GND8 38 Codec VCCA 23 GNDA 26 Digital Peripherals VCC6 VCC7 59 76 GND9 GND10 53 73 Internal logic VCCQ0 VCCQ1 33 96 GNDQ0 GNDQ1 47 104 Phase-Locked Loop (PLL) VCCS 50 GNDS 48 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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