TNETV1647GSTZWT datasheet(230/236 Pages) TI1

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TMS320DM6441

SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

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6.26 IEEE 1149.1 JTAG

The JTAG(3) interface is used for BSDL testing and emulation of the DM6441 device.

The DM6441 device requires that both TRST and RESET be asserted upon power up to be properly

initialized. While RESET initializes the device, TRST initializes the device's emulation logic. Both resets

are required for proper operation.

While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for

the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG

port interface and device's emulation logic in the reset state.

TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or

exercise the device's boundary scan functionality.

RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE

correctly. Other boundary-scan instructions work correctly independent of current state of RESET.

For maximum reliability, DM6441 includes an internal pulldown (IPD) on the TRST pin to ensure that

TRST will always be asserted upon power up and the device's internal emulation logic will always be

properly initialized.

JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG

controllers may not drive TRST high but expect the use of a pullup resistor on TRST.

When using this type of JTAG controller, assert TRST to intialize the device after powerup and externally

drive TRST high before attempting any emulation or boundary scan operations.

Note: The sequencing of all the JTAG signals must follow the IEEE.1149.1 JTAG standard.

6.26.1

JTAG Peripheral Register Description(s) – JTAG ID Register

Table 6-118. JTAG ID Register

HEX ADDRESS RANGE

ACRONYM

COMMENTS

Read-only. Provides 32-bit

0x01C4 0028

JTAGID

JTAG Identification Register

JTAG ID of the device.

(3)

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the

DM6441 device, the JTAG ID register resides at address location 0x01C4 0028. The register hex value for

DM6441 is: 0x0B70 002F for silicon revisions 1.3 and earlier, and 0x1B70 002F for silicon revision

2.1 and later. For the actual register bit names and their associated bit field descriptions, see Figure 6-83

and Table 6-119.

31-28

27-12

11-1

VARIANT

PART NUMBER (16-Bit)

MANUFACTURER (11-Bit)

LSB

(4-Bit)(A)

R-000x

R-1011 0111 0000 0000

R-0000 0010 111

R-1

LEGEND: R = Read, W = Write, n = value at reset

(A) For silicon revisions 1.3 and earlier, VARIANT = 0000. For silicon revision 2.1 and later, VARIANT = 0001.

Figure 6-83. JTAG ID Register Description - DM6441 Register Value - 0xXB70 002F

230

Peripheral and Electrical Specifications

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