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DSPIC33EP128GS708 Datasheet(PDF) 254 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 254 Page - Microchip Technology |
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254 / 484 page  dsPIC33EPXXXGS70X/80X FAMILY DS70005258C-page 254 2016-2018 Microchip Technology Inc. REGISTER 19-3: I2CxSTAT: I2Cx STATUS REGISTER HSC/R-0 HSC/R-0 HSC/R-0 U-0 U-0 HS/R/C-0 HSC/R-0 HSC/R-0 ACKSTAT TRSTAT ACKTIM — — BCL GCSTAT ADD10 bit 15 bit 8 HS/R/C-0 HS/R/C-0 HSC/R-0 HSC/R/C-0 HSC/R/C-0 HSC/R-0 HSC/R-0 HSC/R-0 IWCOL I2COV D_A P S R_W RBF TBF bit 7 bit 0 Legend: C = Clearable bit ‘0’ = Bit is cleared HS = Hardware Settable bit R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation) 1 = NACK was received from slave 0 = ACK was received from slave It is set or cleared by hardware at the end of a slave Acknowledge. bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress It is set by hardware at the beginning of master transmission. It is cleared by hardware at the end of slave Acknowledge. bit 13 ACKTIM: Acknowledge Time Status bit (I2C Slave mode only) 1 = I2C bus is an Acknowledge sequence, set on the 8th falling edge of SCLx 0 = Not an Acknowledge sequence, cleared on the 9th rising edge of SCLx bit 12-11 Unimplemented: Read as ‘0’ bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No bus collision detected It is set by hardware at detection of a bus collision. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received It is set by hardware when address matches the general call address. It is cleared by hardware at Stop detection. bit 8 ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched It is set by hardware at the match of the 2nd byte of the matched 10-bit address. It is cleared by hardware at Stop detection. bit 7 IWCOL: I2Cx Write Collision Detect bit 1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy 0 = No collision It is set by hardware at the occurrence of a write to I2CxTRN while busy (cleared by software). bit 6 I2COV: I2Cx Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register was still holding the previous byte 0 = No overflow It is set by hardware at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software). |
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