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DSPIC33EP128GS708 Datasheet(PDF) 255 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 255 Page - Microchip Technology |
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255 / 484 page ![]() 2016-2018 Microchip Technology Inc. DS70005258C-page 255 dsPIC33EPXXXGS70X/80X FAMILY bit 5 D_A: Data/Address bit (I2C Slave mode only) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was a device address It is cleared by hardware at a device address match. It is set by hardware by reception of a slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last It is set or cleared by hardware when a Start, Repeated Start or Stop is detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last It is set or cleared by hardware when a Start, Repeated Start or Stop is detected. bit 2 R_W: Read/Write Information bit (I2C Slave mode only) 1 = Read – Indicates data transfer is output from the slave 0 = Write – Indicates data transfer is input to the slave It is set or cleared by hardware after reception of an I2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive is complete, I2CxRCV is full 0 = Receive is not complete, I2CxRCV is empty It is set by hardware when I2CxRCV is written with a received byte. It is cleared by hardware when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit is in progress, I2CxTRN is full 0 = Transmit is complete, I2CxTRN is empty It is set by hardware when software writes to I2CxTRN. It is cleared by hardware at completion of a data transmission. REGISTER 19-3: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) |
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