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DSPIC33EP128GS708 Datasheet(PDF) 290 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 290 Page - Microchip Technology |
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290 / 484 page  dsPIC33EPXXXGS70X/80X FAMILY DS70005258C-page 290 2016-2018 Microchip Technology Inc. REGISTER 22-11: ADCORExL: DEDICATED ADC CORE x CONTROL REGISTER LOW (x = 0 to 3) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — SAMC<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SAMC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 SAMC<9:0>: Dedicated ADC Core x Conversion Delay Selection bits These bits determine the time between the trigger event and the start of conversion in the number of the Core Clock Periods (TADCORE). During this time, the ADC Core x still continues sampling. This feature is enabled by the SAMCxEN bits in the ADCON4L register. 1111111111 = 1025 TADCORE • • • 0000000001 = 3 TADCORE 0000000000 = 2 TADCORE |
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