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DSPIC33EP128GS708 Datasheet(PDF) 286 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 286 Page - Microchip Technology |
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286 / 484 page ![]() dsPIC33EPXXXGS70X/80X FAMILY DS70005258C-page 286 2016-2018 Microchip Technology Inc. REGISTER 22-7: ADCON4L: ADC CONTROL REGISTER 4 LOW U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — SAMC3EN SAMC2EN SAMC1EN SAMC0EN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 SAMC3EN: Dedicated ADC Core 3 Conversion Delay Enable bit 1 = After trigger, the conversion will be delayed and the ADC core will continue sampling during the time specified by the SAMC<9:0> bits in the ADCORE3L register 0 = After trigger, the sampling will be stopped immediately and the conversion will be started on the next core clock cycle bit 2 SAMC2EN: Dedicated ADC Core 2 Conversion Delay Enable bit 1 = After trigger, the conversion will be delayed and the ADC core will continue sampling during the time specified by the SAMC<9:0> bits in the ADCORE2L register 0 = After trigger, the sampling will be stopped immediately and the conversion will be started on the next core clock cycle bit 1 SAMC1EN: Dedicated ADC Core 1 Conversion Delay Enable bit 1 = After trigger, the conversion will be delayed and the ADC core will continue sampling during the time specified by the SAMC<9:0> bits in the ADCORE1L register 0 = After trigger, the sampling will be stopped immediately and the conversion will be started on the next core clock cycle bit 0 SAMC0EN: Dedicated ADC Core 0 Conversion Delay Enable bit 1 = After trigger, the conversion will be delayed and the ADC core will continue sampling during the time specified by the SAMC<9:0> bits in the ADCORE0L register 0 = After trigger, the sampling will be stopped immediately and the conversion will be started on the next core clock cycle |
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