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DSPIC33EP128GS708 Datasheet(PDF) 285 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 285 Page - Microchip Technology |
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285 / 484 page  2016-2018 Microchip Technology Inc. DS70005258C-page 285 dsPIC33EPXXXGS70X/80X FAMILY REGISTER 22-6: ADCON3H: ADC CONTROL REGISTER 3 HIGH R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CLKSEL1 CLKSEL0 CLKDIV5 CLKDIV4 CLKDIV3 CLKDIV2 CLKDIV1 CLKDIV0 bit 15 bit 8 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 SHREN — — — C3ENC2ENC1ENC0EN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 CLKSEL<1:0>: ADC Module Clock Source Selection bits 11 = APLL 10 = FRC 01 = FOSC (System Clock x 2) 00 = FSYS (System Clock) bit 13-8 CLKDIV<5:0>: ADC Module Clock Source Divider bits The divider forms a TCORESRC clock used by all ADC cores (shared and dedicated) from the TSRC ADC module clock source selected by the CLKSEL<1:0> bits. Then, each ADC core individually divides the TCORESRC clock to get a core-specific TADCORE clock using the ADCS<6:0> bits in the ADCORExH register or the SHRADCS<6:0> bits in the ADCON2L register. 111111 = 64 Source Clock Periods • • • 000011 = 4 Source Clock Periods 000010 = 3 Source Clock Periods 000001 = 2 Source Clock Periods 000000 = 1 Source Clock Period bit 7 SHREN: Shared ADC Core Enable bit 1 = Shared ADC core is enabled 0 = Shared ADC core is disabled bit 6-4 Unimplemented: Read as ‘0’ bit 3 C3EN: Dedicated ADC Core 3 Enable bits 1 = Dedicated ADC Core 3 is enabled 0 = Dedicated ADC Core 3 is disabled bit 2 C2EN: Dedicated ADC Core 2 Enable bits 1 = Dedicated ADC Core 2 is enabled 0 = Dedicated ADC Core 2 is disabled bit 1 C1EN: Dedicated ADC Core 1 Enable bits 1 = Dedicated ADC Core 1 is enabled 0 = Dedicated ADC Core 1 is disabled bit 0 C0EN: Dedicated ADC Core 0 Enable bits 1 = Dedicated ADC Core 0 is enabled 0 = Dedicated ADC Core 0 is disabled |
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