DSPIC33EP128GS708 datasheet(289/484 Pages) MICROCHIP

289 / 484 page

 2016-2018 Microchip Technology Inc.

DS70005258C-page 289

dsPIC33EPXXXGS70X/80X FAMILY

U-0

R/W-0

—

WARMTIME<3:0>

bit 15

bit 8

R/W-0

U-0

R/W-0

SHRCIE

—

C3CIE

C2CIE

C1CIE

C0CIE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-12

Unimplemented: Read as ‘0’

bit 11-8

WARMTIME<3:0>: ADC Dedicated Core x Power-up Delay bits

These bits determine the power-up delay in the number of the Core Source Clock Periods (TCORESRC)

for all ADC cores.

1111 = 32768 Source Clock Periods

1110 = 16384 Source Clock Periods

1101 = 8192 Source Clock Periods

1100 = 4096 Source Clock Periods

1011 = 2048 Source Clock Periods

1010 = 1024 Source Clock Periods

1001 = 512 Source Clock Periods

1000 = 256 Source Clock Periods

0111 = 128 Source Clock Periods

0110 = 64 Source Clock Periods

0101 = 32 Source Clock Periods

0100 = 16 Source Clock Periods

00xx = 16 Source Clock Periods

bit 7

SHRCIE: Shared ADC Core Ready Common Interrupt Enable bit

1 = Common interrupt will be generated when ADC core is powered and ready for operation

0 = Common interrupt is disabled for an ADC core ready event

bit 6-4

Unimplemented: Read as ‘0’

bit 3

C3CIE: Dedicated ADC Core 3 Ready Common Interrupt Enable bit

1 = Common interrupt will be generated when ADC Core 3 is powered and ready for operation

0 = Common interrupt is disabled for an ADC Core 3 ready event

bit 2

C2CIE: Dedicated ADC Core 2 Ready Common Interrupt Enable bit

1 = Common interrupt will be generated when ADC Core 2 is powered and ready for operation

0 = Common interrupt is disabled for an ADC Core 2 ready event

bit 1

C1CIE: Dedicated ADC Core 1 Ready Common Interrupt Enable bit

1 = Common interrupt will be generated when ADC Core 1 is powered and ready for operation

0 = Common interrupt is disabled for an ADC Core 1 ready event

bit 0

C0CIE: Dedicated ADC Core 0 Ready Common Interrupt Enable bit

1 = Common interrupt will be generated when ADC Core 0 is powered and ready for operation

0 = Common interrupt is disabled for an ADC Core 0 ready event

DSPIC33EP128GS708 Datasheet(PDF) 289 Page - Microchip Technology

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