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DSPIC33EP128GS708 Datasheet(PDF) 288 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 288 Page - Microchip Technology |
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288 / 484 page  dsPIC33EPXXXGS70X/80X FAMILY DS70005258C-page 288 2016-2018 Microchip Technology Inc. REGISTER 22-9: ADCON5L: ADC CONTROL REGISTER 5 LOW HSC/R-0 U-0 U-0 U-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 SHRRDY — — — C3RDY C2RDY C1RDY C0RDY bit 15 bit 8 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 SHRPWR — — — C3PWR C2PWR C1PWR C0PWR bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SHRRDY: Shared ADC Core Ready Flag bit 1 = ADC core is powered and ready for operation 0 = ADC core is not ready for operation bit 14-12 Unimplemented: Read as ‘0’ bit 11 C3RDY: Dedicated ADC Core 3 Ready Flag bit 1 = ADC core is powered and ready for operation 0 = ADC core is not ready for operation bit 10 C2RDY: Dedicated ADC Core 2 Ready Flag bit 1 = ADC core is powered and ready for operation 0 = ADC core is not ready for operation bit 9 C1RDY: Dedicated ADC Core 1 Ready Flag bit 1 = ADC core is powered and ready for operation 0 = ADC core is not ready for operation bit 8 C0RDY: Dedicated ADC Core 0 Ready Flag bit 1 = ADC core is powered and ready for operation 0 = ADC core is not ready for operation bit 7 SHRPWR: Shared ADC Core x Power Enable bit 1 = ADC Core x is powered 0 = ADC Core x is off bit 6-4 Unimplemented: Read as ‘0’ bit 3 C3PWR: Dedicated ADC Core 3 Power Enable bit 1 = ADC core is powered 0 = ADC core is off bit 2 C2PWR: Dedicated ADC Core 2 Power Enable bit 1 = ADC core is powered 0 = ADC core is off bit 1 C1PWR: Dedicated ADC Core 1 Power Enable bit 1 = ADC core is powered 0 = ADC core is off bit 0 C0PWR: Dedicated ADC Core 0 Power Enable bit 1 = ADC core is powered 0 = ADC core is off |
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