DSPIC33EP128GS708 datasheet(284/484 Pages) MICROCHIP

284 / 484 page

dsPIC33EPXXXGS70X/80X FAMILY

DS70005258C-page 284

 2016-2018 Microchip Technology Inc.

ADCON3L: ADC CONTROL REGISTER 3 LOW

R/W-0

HSC/R-0

R/W-0

HSC/R-0

REFSEL2

REFSEL1

REFSEL0

SUSPEND

SUSPCIE

SUSPRDY

SHRSAMP

CNVRTCH

bit 15

bit 8

R/W-0

HSC/R/W-0

R/W-0

SWLCTRG

SWCTRG

CNVCHSEL5 CNVCHSEL4 CNVCHSEL3 CNVCHSEL2 CNVCHSEL1 CNVCHSEL0

bit 7

bit 0

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

W = Writable bit

HSC = Hardware Settable/Clearable bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-13

REFSEL<2:0>: ADC Reference Voltage Selection bits

001-111 = Unimplemented: Do not use

bit 12

SUSPEND: All ADC Cores Triggers Disable bit

1 = All new trigger events for all ADC cores are disabled

0 = All ADC cores can be triggered

bit 11

SUSPCIE: Suspend All ADC Cores Common Interrupt Enable bit

1 = Common interrupt will be generated when ADC core triggers are suspended (SUSPEND bit = 1)

and all previous conversions are finished (SUSPRDY bit becomes set)

0 = Common interrupt is not generated for suspend ADC cores event

bit 10

SUSPRDY: All ADC Cores Suspended Flag bit

1 = All ADC cores are suspended (SUSPEND bit = 1) and have no conversions in progress

0 = ADC cores have previous conversions in progress

bit 9

SHRSAMP: Shared ADC Core Sampling Direct Control bit

This bit should be used with the individual channel conversion trigger controlled by the CNVRTCH bit.

It connects an analog input, specified by the CNVCHSEL<5:0> bits, to the shared ADC core and allows

extending the sampling time. This bit is not controlled by hardware and must be cleared before the

conversion starts (setting CNVRTCH to ‘1’).

1 = Shared ADC core samples an analog input specified by the CNVCHSEL<5:0> bits

0 = Sampling is controlled by the shared ADC core hardware

bit 8

CNVRTCH: Software Individual Channel Conversion Trigger bit

1 = Single trigger is generated for an analog input specified by the CNVCHSEL<5:0> bits; when the bit

is set, it is automatically cleared by hardware on the next instruction cycle

0 = Next individual channel conversion trigger can be generated

bit 7

SWLCTRG: Software Level-Sensitive Common Trigger bit

1 = Triggers are continuously generated for all channels with the software, level-sensitive common

trigger selected as a source in the ADTRIGxL and ADTRIGxH registers

0 = No software, level-sensitive common triggers are generated

bit 6

SWCTRG: Software Common Trigger bit

1 = Single trigger is generated for all channels with the software, common trigger selected as a source

in the ADTRIGxL and ADTRIGxH registers; when the bit is set, it is automatically cleared by

hardware on the next instruction cycle

0 = Ready to generate the next software common trigger

bit 5-0

CNVCHSEL <5:0>: Channel Number Selection for Software Individual Channel Conversion Trigger bits

These bits define a channel to be converted when the CNVRTCH bit is set.

Value

VREFH

VREFL

000

AVDD

AVSS

DSPIC33EP128GS708 Datasheet(PDF) 284 Page - Microchip Technology

DSPIC33EP128GS708 Datasheet(HTML) 284 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL