DSPIC33EP128GS708 datasheet(282/484 Pages) MICROCHIP

282 / 484 page

dsPIC33EPXXXGS70X/80X FAMILY

DS70005258C-page 282

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ADCON2L: ADC CONTROL REGISTER 2 LOW

R/W-0

r-0

R/W-0

r-0

R/W-0

REFCIE

REFERCIE

—EIEN

—

SHREISEL2(1) SHREISEL1(1) SHREISEL0(1)

bit 15

bit 8

U-0

R/W-0

—

SHRADCS<6:0>

bit 7

bit 0

Legend:

r = Reserved bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

REFCIE: Band Gap and Reference Voltage Ready Common Interrupt Enable bit

1 = Common interrupt will be generated when the band gap will become ready

0 = Common interrupt is disabled for the band gap ready event

bit 14

REFERCIE: Band Gap or Reference Voltage Error Common Interrupt Enable bit

1 = Common interrupt will be generated when a band gap or reference voltage error is detected

0 = Common interrupt is disabled for the band gap and reference voltage error event

bit 13

Reserved: Maintain as ‘0’

bit 12

EIEN: Early Interrupts Enable bit

1 = The early interrupt feature is enabled for the input channel interrupts (when the EISTATx flag is set)

0 = The individual interrupts are generated when conversion is done (when the ANxRDY flag is set)

bit 11

Reserved: Maintain as ‘0’

bit 10-8

SHREISEL<2:0>: Shared Core Early Interrupt Time Selection bits(1)

111 = Early interrupt is set and interrupt is generated eight TADCORE clocks prior to when the data is ready

110 = Early interrupt is set and interrupt is generated seven TADCORE clocks prior to when the data is ready

101 = Early interrupt is set and interrupt is generated six TADCORE clocks prior to when the data is ready

100 = Early interrupt is set and interrupt is generated five TADCORE clocks prior to when the data is ready

011 = Early interrupt is set and interrupt is generated four TADCORE clocks prior to when the data is ready

010 = Early interrupt is set and interrupt is generated three TADCORE clocks prior to when the data is ready

001 = Early interrupt is set and interrupt is generated two TADCORE clocks prior to when the data is ready

000 = Early interrupt is set and interrupt is generated one TADCORE clock prior to when the data is ready

bit 7

Unimplemented: Read as ‘0’

bit 6-0

SHRADCS<6:0>: Shared ADC Core Input Clock Divider bits

These bits determine the number of TCORESRC (Source Clock Periods) for one shared TADCORE (Core

Clock Period).

1111111 = 254 Source Clock Periods

•

0000011 = 6 Source Clock Periods

0000010 = 4 Source Clock Periods

0000001 = 2 Source Clock Periods

0000000 = 2 Source Clock Periods

Note 1:

For the 6-bit shared ADC core resolution (SHRRES<1:0> = 00), the SHREISEL<2:0> settings,

from ‘100’ to ‘111’, are not valid and should not be used. For the 8-bit shared ADC core resolution

(SHRRES<1:0> = 01), the SHREISEL<2:0> settings, ‘110’ and ‘111’, are not valid and should not be used.

DSPIC33EP128GS708 Datasheet(PDF) 282 Page - Microchip Technology

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