DSPIC33EP128GS708 datasheet(305/484 Pages) MICROCHIP

305 / 484 page

 2016-2018 Microchip Technology Inc.

DS70005258C-page 305

dsPIC33EPXXXGS70X/80X FAMILY

HS/R/W-0

U-0

r-0

R/W-0

CSHRRDY

—

CSHRDIFF

CSHREN

CSHRRUN

bit 15

bit 8

U-0

—

bit 7

bit 0

Legend:

r = Reserved bit

U = Unimplemented bit, read as ‘0’

R = Readable bit

W = Writable bit

HS = Hardware Settable bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

CSHRRDY: Shared ADC Core Calibration Status Flag bit

1 = Shared ADC core calibration is finished

0 = Shared ADC core calibration is in progress

bit 14-12

Unimplemented: Read as ‘0’

bit 11

Reserved: Maintain as ‘0’

bit 10

CSHRDIFF: Shared ADC Core Differential-Mode Calibration bit

1 = Shared ADC core will be calibrated in Differential Input mode

0 = Shared ADC core will be calibrated in Single-Ended Input mode

bit 9

CSHREN: Shared ADC Core Calibration Enable bit

1 = Shared ADC core calibration bits (CSHRRDY, CSHRDIFF and CSHRRUN) can be accessed by

software

0 = Shared ADC core calibration bits are disabled

bit 8

CSHRRUN: Shared ADC Core Calibration Start bit

1 = If this bit is set by software, the shared ADC core calibration cycle is started; this bit is cleared

automatically by hardware

0 = Software can start the next calibration cycle

bit 7-0

Unimplemented: Read as ‘0’

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