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DSPIC33EP128GS708 Datasheet(PDF) 308 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 308 Page - Microchip Technology |
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308 / 484 page  dsPIC33EPXXXGS70X/80X FAMILY DS70005258C-page 308 2016-2018 Microchip Technology Inc. REGISTER 22-34: ADFLxCON: ADC DIGITAL FILTER x CONTROL REGISTER (x = 0 or 1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HSC/R-0 FLEN MODE1 MODE0 OVRSAM2 OVRSAM1 OVRSAM0 IE RDY bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FLCHSEL<4:0> bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLEN: Filter Enable bit 1 = Filter is enabled 0 = Filter is disabled and the RDY bit is cleared bit 14-13 MODE<1:0>: Filter Mode bits 11 = Averaging mode 10 = Reserved 01 = Reserved 00 = Oversampling mode bit 12-10 OVRSAM<2:0>: Filter Averaging/Oversampling Ratio bits If MODE<1:0> = 00: 111 = 128x (16-bit result in the ADFLxDAT register is in 12.4 format) 110 = 32x (15-bit result in the ADFLxDAT register is in 12.3 format) 101 = 8x (14-bit result in the ADFLxDAT register is in 12.2 format) 100 = 2x (13-bit result in the ADFLxDAT register is in 12.1 format) 011 = 256x (16-bit result in the ADFLxDAT register is in 12.4 format) 010 = 64x (15-bit result in the ADFLxDAT register is in 12.3 format) 001 = 16x (14-bit result in the ADFLxDAT register is in 12.2 format) 000 = 4x (13-bit result in the ADFLxDAT register is in 12.1 format) If MODE<1:0> = 11 (12-bit result in the ADFLxDAT register in all instances): 111 = 256x 110 = 128x 101 = 64x 100 = 32x 011 = 16x 010 = 8x 001 = 4x 000 = 2x bit 9 IE: Filter Common ADC Interrupt Enable bit 1 = Common ADC interrupt will be generated when the filter result will be ready 0 = Common ADC interrupt will not be generated for the filter bit 8 RDY: Oversampling Filter Data Ready Flag bit This bit is cleared by hardware when the result is read from the ADFLxDAT register. 1 = Data in the ADFLxDAT register is ready 0 = The ADFLxDAT register has been read and new data in the ADFLxDAT register is not ready bit 7-5 Unimplemented: Read as ‘0’ |
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