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DSPIC33EP128GS708 Datasheet(PDF) 306 Page - Microchip Technology

Part # DSPIC33EP128GS708
Description  16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators
PDF  484 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DSPIC33EP128GS708 Datasheet(HTML) 306 Page - Microchip Technology

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dsPIC33EPXXXGS70X/80X FAMILY
DS70005258C-page 306
 2016-2018 Microchip Technology Inc.
REGISTER 22-31: ADCMPxCON: ADC DIGITAL COMPARATOR x CONTROL REGISTER (x = 0 or 1)
U-0
U-0
U-0
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
—
—
—
CHNL<4:0>
bit 15
bit 8
R/W-0
R/W-0
HC/HS/R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMPEN
IE
STAT
BTWN
HIHI
HILO
LOHI
LOLO
bit 7
bit 0
Legend:
HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
HS = Hardware Settable bit
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
CHNL<4:0>: Input Channel Number bits
If the comparator has detected an event for a channel, this channel number is written to these bits.
11111 = Reserved
•
•
10110 = Reserved
10101 = AN21
10100 = AN20
•
•
00001 = AN1
00000 = AN0
bit 7
CMPEN: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled and the STAT status bit is cleared
bit 6
IE: Comparator Common ADC Interrupt Enable bit
1 = Common ADC interrupt will be generated if the comparator detects a comparison event
0 = Common ADC interrupt will not be generated for the comparator
bit 5
STAT: Comparator Event Status bit
This bit is cleared by hardware when the channel number is read from the CHNL<4:0> bits.
1 = A comparison event has been detected since the last read of the CHNL<4:0> bits
0 = A comparison event has not been detected since the last read of the CHNL<4:0> bits
bit 4
BTWN: Between Low/High Comparator Event bit
1 = Generates a comparator event when ADCMPxLO ≤ ADCBUFx < ADCMPxHI
0 = Does not generate a digital comparator event when ADCMPxLO ≤ ADCBUFx < ADCMPxHI
bit 3
HIHI: High/High Comparator Event bit
1 = Generates a digital comparator event when ADCBUFx ≥ ADCMPxHI
0 = Does not generate a digital comparator event when ADCBUFx ≥ ADCMPxHI
bit 2
HILO: High/Low Comparator Event bit
1 = Generates a digital comparator event when ADCBUFx < ADCMPxHI
0 = Does not generate a digital comparator event when ADCBUFx < ADCMPxHI
bit 1
LOHI: Low/High Comparator Event bit
1 = Generates a digital comparator event when ADCBUFx ≥ ADCMPxLO
0 = Does not generate a digital comparator event when ADCBUFx ≥ ADCMPxLO
bit 0
LOLO: Low/Low Comparator Event bit
1 = Generates a digital comparator event when ADCBUFx < ADCMPxLO
0 = Does not generate a digital comparator event when ADCBUFx < ADCMPxLO



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