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S75WS256NDFBAWMB Datasheet(PDF) 131 Page - SPANSION |
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S75WS256NDFBAWMB Datasheet(HTML) 131 Page - SPANSION |
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131 / 216 page  February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 129 Data Sheet 25.3 Synchronous/Burst Read Notes: 1. Addresses are latched on the first rising edge of CLK. 2. Not 100% tested. Parameter Description 80 MHz 66 MHz 54 MHz Unit JEDEC Standard tIACC Latency Max 148 ns tBACC Burst Access Time Valid Clock to Output Delay Max 9.1 11.2 13.5 ns tACS Address Setup Time to CLK (Note 1)Min 4 4 5 ns tACH Address Hold Time from CLK (Note 1)Min 2 2 3 ns tBDH Data Hold Time from Next Clock Cycle Min 4 4 5 ns tCR Chip Enable to RDY Valid Max 9.1 11.2 13.5 ns tOE Output Enable to Output Valid Max 9.1 11.2 13.5 ns tCEZ Chip Enable to High Z (Note 2) Max 10 10 10 ns tOEZ Output Enable to High Z (Note 2) Max 10 10 10 ns tCES CE# Setup Time to CLK Min 4 4 4 ns tRDYS RDY Setup Time to CLK Min 4 4 5 ns tRACC Ready Access Time from CLK Max 9.1 11.2 13.5 ns tAAS Address Setup Time to AVD# (Note 1)Min 4 4 5 ns tAAH Address Hold Time to AVD# (Note 1)Min 2 2 3 ns tCAS CE# Setup Time to AVD# Min 0 0 0 ns tAVC AVD# Low to CLK Min 4 4 4 ns tAVD AVD# Pulse Min 8 8 8 ns |
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