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S75WS256NDFBAWMB Datasheet(PDF) 134 Page - SPANSION |
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S75WS256NDFBAWMB Datasheet(HTML) 134 Page - SPANSION |
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134 / 216 page  132 S75WS256Nxx Based MCPs S75WS-N-00_00_A0 February 17, 2005 Data Sheet Notes: 1. Figure assumes eleven wait states for initial access and synchronous read. 2. The Set Configuration Register command sequence has been written with A18=0; device will output RDY one cycle before valid data. Figure 25.6 Burst with RDY Set One Cycle Before Data 25.4 Asynchronous Mode Read @ VIO = 1.8 V Notes: 1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#. 2. Not 100% tested. Parameter Description 80 MHz 66 MHz 54 MHz Unit JEDEC Standard tCE Access Time from CE# Low Max 148 ns tACC Asynchronous Access Time (Note 1) Max 143 ns tAVDP AVD# Low Time Min 8 8 10 ns tAAVDS Address Setup Time to Rising Edge of AVD# Min 4 4 5 ns tAAVDH Address Hold Time from Rising Edge of AVD# Min 2 2 3 ns tOE Output Enable to Output Valid Max 9.1 11.2 13.5 ns tOEH Output Enable Hold Time Read Min 0 0 0 ns Data# Polling Min 10 10 10 ns tOEZ Output Enable to High Z (Note 2) Max 10 10 10 ns tCAS CE# Setup Time to AVD# Min 0 0 0 ns Da+1 Da Da+2 Da+3 Da + n OE# Data Addresses Aa AVD# RDY CLK CE# tCES tACS tAVC tAVD tACH tOE tRACC tOEZ tCEZ tIACC tBDH 12 wait cycles for initial access shown. Hi-Z Hi-Z Hi-Z 1 2 3 4 10 11 tRDYS tBACC tCR |
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