S75WS256NDFBAWMB datasheet(206/216 Pages) SPANSION

206 / 216 page

204

S75WS256Nxx Based MCPs

S75WS-N-00_A0 February 17, 2005

Ad van c e

Inf o rmation

Notes:

1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.

2. When transitioning between asynchronous and variable-latency burst operations, CE# must go High. If CE# goes High, it must remain High

for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See How Extended Timings Impact CellularRAM™ Operation

for restrictions on the maximum CE# Low time (tCEM).

Figure 34.23. Burst Read Followed by Asynchronous Write (WE#-Controlled)

Valid

Address

tSP

tHD

tOHZ

High-Z

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

A[22:0]

ADV#

CE#

DQ[15:0]

WAIT

tHD

tWC

VIH

VIL

OE#

WE#

tCLK

VIH

VIL

CLK

tSP tHD

(Note 2)

tWP

tWPH

tSP

tHD

Valid

Output

tCBPH

tKOH

tACLK

Don't Care

Undefined

Legend:

Valid

Address

VIH

VIL

LB#/UB#

tOLZ

tAW

tWR

tCSP

tBW

tDH

tKHTL

tDW

tSP

tHD

tHZ

tBOE

tCEM

tCW

tAS

tCEW

tHZ

READ Burst Identified

(WE# = HIGH)

High-Z

Valid

Input

S75WS256NDFBAWMB Datasheet(PDF) 206 Page - SPANSION

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