S75WS256NDFBAWMB datasheet(202/216 Pages) SPANSION

202 / 216 page

200

S75WS256Nxx Based MCPs

S75WS-N-00_A0 February 17, 2005

Ad van c e

Inf o rmation

Table 34.18 Read Timing Parameters—Burst Write Followed by Burst Read

Symbol

70ns/80 MHz

85ns/66 MHz

Units

Min

Max

Min

Max

tACLK

911

tBOE

tCLK

12.5

tCSP

tHD

tKOH

tOHZ

tSP

Notes:

1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.

1. When transitioning between asynchronous and variable-latency burst operations, CE# must go High. If CE# goes High, it must remain High

for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See How Extended Timings Impact CellularRAM™ Operation

for restrictions on the maximum CE# Low time (tCEM).

Figure 34.18 Asynchronous Write Followed by Burst Read

tOHZ

High-Z

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

A[22:0]

ADV#

CE#

LB#/UB#

DQ[15:0]

WAIT

tCSP

tSP

tHD

VIH

VIL

OE#

WE#

tSP

tHD

tCLK

VIH

VIL

CLK

tBOE

Valid

Address

tWC

(Note 2)

tWP tWPH

tSP

tHD

Valid

Output

Valid

Output

Valid

Output

Valid

Output

VOH

VOL

tKOH

tACLK

High-Z

Don't Care

Undefined

Legend:

Valid

Address

Valid

Address

tCKA

tSP

tHD

tBW

tCW

tAW

tWR

tCBPH

tWC

tCEW

DATA

tWHZ

DATA

tVPH

tAVS

tAVH

tVP

tVS

tCVS

tAS

tDH

tDW

S75WS256NDFBAWMB Datasheet(PDF) 202 Page - SPANSION

S75WS256NDFBAWMB Datasheet(HTML) 202 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL