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S75WS256NDFBAWMB Datasheet(PDF) 201 Page - SPANSION

Part # S75WS256NDFBAWMB
Description  Stacked Multi-Chip Product (MCP)
PDF  216 Pages
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Manufacturer  SPANSION [SPANSION]
Direct Link  http://www.spansion.com
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S75WS256NDFBAWMB Datasheet(HTML) 201 Page - SPANSION

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February 17, 2005 S75WS-N-00_A0
S75WS256Nxx Based MCPs
199
Advance
Information
Table 34.16 Burst Write Timing Parameters—BCR[8] = 0
Symbol
70ns/80 MHz
85ns/66 MHz
Units
Min
Max
Min
Max
tCLK
12.5
15
ns
tHD
22
ns
tKHTL
811
ns
tSP
33
ns
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
1. To allow self-refresh operations to occur between transactions, CE# must remain High for at least 5ns (tCBPH) to schedule the appropriate
internal refresh operation. CE# can stay Low between burst Read and burst Write operations. See How Extended Timings Impact
CellularRAM™ Operation for restrictions on the maximum CE# Low time (tCEM).
Figure 34.17 Burst Write Followed by Burst Read
Table 34.17 Write Timing Parameters—Burst Write Followed by Burst Read
Symbol
70ns/80 MHz
85ns/66 MHz
Units
Min
Max
Min
Max
tCBPH
55
ns
tCLK
12.5
20
15
20
ns
tCSP
4
20520
ns
tHD
22
ns
tSP
33
ns
tOHZ
High-Z
High-Z
tCBPH
High-Z
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
A[22:0]
ADV#
CE#
LB#/UB#
DQ[15:0]
WAIT
tSP
tCSP
tSP
tHD
tHD
VIH
VIL
OE#
WE#
tSP tHD
tCLK
VIH
VIL
CLK
tHD
tBOE
Valid
Address
tSP
tHD
Valid
Address
tSP
tHD
(Note 2) tCSP
tSP tHD
tSP
tHD
D[0]
D[3]
D[2]
D[1]
Valid
Output
Valid
Output
Valid
Output
Valid
Output
VOH
VOL
tKOH
tACLK
tSP tHD
High-Z
Don't Care
Undefined
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