IIS2DULPX datasheet(46/106 Pages) STMICROELECTRONICS

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8.10

FIFO_CTRL (15h)

R/W

CFG_CHG_EN

FIFO_

DEPTH

DIS_HARD_

RST_CS

0(1)

STOP_ON

_FTH

FIFO_MODE2

FIFO_MODE1

FIFO_MODE0

1. This bit must be set to 0 for the correct operation of the device.

Table 41. FIFO_CTRL register description

CFG_CHG_EN

Enables batching in FIFO of the device configuration and timestamp value when the ODR (output data

rate) or the BDR (batch data rate) changes. Default value: 0

(0: disabled; 1: enabled)

FIFO_DEPTH

If 1, enables 2x depth mode for FIFO buffer.

DIS_HARD_RST_CS

If this bit is set to 0 and the power-up sequence has been performed over the I²C/I3C interface,

resetting the CS pin is equivalent to performing a deep power-off command (see Section 3.3.3: Deep

power-off command). Otherwise, if this bit is set to 1, resetting the CS pin has no effect.

Default value: 0

STOP_ON_FTH

Sensing chain FIFO stop values memorization at threshold level.

(0: FIFO depth is not limited (default);

1: FIFO depth is limited to threshold level)

FIFO_MODE[2:0](1)

Different FIFO modes are enabled as shown in Table 42.

1. The user must set the FIFO_EN bit to 1 in the CTRL4 (13h) register before setting the FIFO_MODE[2:0] bits.

Table 42. Selection of FIFO mode

FIFO_MODE2 FIFO_MODE1 FIFO_MODE0

Mode

Bypass mode

FIFO mode: stops collecting data when FIFO is full

Reserved

Continuous-to-FIFO: stream mode until the trigger is deasserted, then FIFO

mode

Bypass-to-continuous: bypass mode until the trigger is deasserted, then

continuous mode

Reserved

Continuous mode: if the FIFO is full, the new sample overwrites the older

sample.

Bypass-to-FIFO: bypass mode until the trigger is deasserted, then FIFO

mode

IIS2DULPX

DS14580 - Rev 1

page 46/106

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