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IIS2DULPX Datasheet(PDF) 8 Page - STMicroelectronics |
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IIS2DULPX Datasheet(HTML) 8 Page - STMicroelectronics |
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8 / 106 page  2.4 Communication interface characteristics 2.4.1 SPI - serial peripheral interface Subject to general operating conditions for VDD and Top. Table 6. SPI target timing values Symbol Parameter Value(1) Unit Min Typ Max fc(SPC) SPI clock frequency 10 MHz tc(SPC) SPI clock period 100 ns thigh(SPC) SPI clock high 45 tlow(SPC) SPI clock low 45 tsu(CS) CS setup time (mode 3) 5 CS setup time (mode 0) 20 th(CS) CS hold time (mode 3) 20 CS hold time (mode 0) 20 tsu(SI) SDI input setup time 7 th(SI) SDI input hold time 15 tv(SO) SDO valid output time 25 tdis(SO) SDO output disable time 50 Cload Bus capacitance 100 pF 1. Values are evaluated at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production Figure 3. SPI target timing in mode 0 CS SPC SDI SDO MSB OUT MSB IN LSB OUT LSB IN t t t tlow(SPC) v(SO) tc(SPC) thigh(SPC) tsu(CS) th(SI) tsu(SI) dis(SO) h(CS) IIS2DULPX Mechanical and electrical specifications DS14580 - Rev 1 page 8/106 |
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