IIS2DULPX datasheet(4/106 Pages) STMICROELECTRONICS

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1.2

Pin description

Figure 2. Pin connections

GND

RES/EXT_CLK

SCL/SPC

SDO/TA0

SDA/SDI/SDO

(TOPVIEW)

DIRECTION OF THE

DETECTABLE

ACCELERATIONS

VDD

(BOTTOM VIEW)

VDDIO

Table 1. Pin description

Pin#

Name

Function

SCL

SPC

I²C/MIPI I3C® serial clock (SCL)

SPI serial port clock (SPC)

2(1)

SPI/I²C/MIPI I3C® mode selection

(1: SPI idle mode / I²C/MIPI I3C® enabled;

0: SPI enabled / I²C/MIPI I3C® disabled)

3(2)

SDO

TA0

SPI serial data output (SDO)

I²C less significant bit of the device address (TA0)

4(2)

SDA

SDI

SDO

I²C/MIPI I3C® serial data (SDA)

SPI serial data input (SDI)

3-wire interface serial data output (SDO)

Internally not connected. Can be tied to VDD, VDDIO, or GND.

GND

0 V supply

RES/EXT_CLK

Connect to GND if not used as interrupt pin 1(3) or as

External clock for the synchronization of multiple sensors(4)

GND

0 V supply

VDD

Power supply

VDDIO

Power supply for I/O pins

11(5)

INT2

Interrupt pin 2. Clock input when selected in one-shot mode. AH input 2 (or Qvar electrode 2) is connected if the analog hub (or Qvar functionality) is

enabled.

12(5)

INT1

Interrupt pin 1. AH input 1 (or Qvar electrode 1) is connected if the analog hub (or Qvar functionality) is enabled.

1. The CS pin is internally pulled up by default. The pull-up of the CS pin can be disconnected by setting the bit CS_PU_DIS of register

PIN_CTRL (0Ch) to 1.

2. The internal pull-up of the SDO/TA0 and SDA/SDI/SDO pins is disconnected by default. The pull-up of the SDO/TA0 pin can be enabled by

setting bit SDO_PU_EN of register PIN_CTRL (0Ch) to 1. The pull-up of the SDA/SDI/SDO pin can be enabled by setting bit SDA_PU_EN

of register PIN_CTRL (0Ch) to 1.

3. When the INT1_ON_RES bit of register CTRL1 (10h) is set to 1, the interrupt signals configured on the INT1 pin are routed to the

RES/EXT_CLK pin.

4. When the external clock for the synchronization of multiple sensors is used, the EXT_CLK_EN bit must be set to 1 in register

EXT_CLK_CFG (08h) and the bit INT1_ON_RES set to 0 in register CTRL1 (10h) in order to correctly drive the pin.

5. The INT1 and INT2 pins are internally pulled down by default. The internal pull-down of the INT1 pin can be disconnected by setting the

PD_DIS_INT1 bit in PIN_CTRL (0Ch) to 1. The internal pull-down of the INT2 pin can be disconnected by setting the PD_DIS_INT2 bit in

PIN_CTRL (0Ch) to 1.

IIS2DULPX

Block diagram and pin description

DS14580 - Rev 1

page 4/106

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