TMP89FS60 datasheet(147/410 Pages) TOSHIBA

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Page 133

TMP89FS60

RA001

11. Divider Output (DVO)

This function outputs approximately 50% duty pulses that can be used to drive the piezoelectric buzzer or other

device.

11.1 Configuration

Figure 11-1 Divider Output

11.2 Control

The divider output is controlled by the divider output control register (DVOCR).

Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]

Note 2: DVOCR<DVOEN> is cleared to "0" when the operation is switched to STOP or IDLE0/SLEEP0 mode. DVOCR<DVOCK>

holds the value.

Note 3: When SYSCR1<DV9CK> is "1" in the NORMAL 1/2 or IDLE 1/2 mode, the DVO frequency is subject to some fluctuations

to synchronize fs and fcgck.

Note 4: Bits 7 to 3 of DVOCR are read as "0".

11.2.1 Function

Select the divider output frequency at DVOCR<DVOCK>.

Divider output control register

DVOCR

(0x0038)

76543

210

Bit Symbol

-----

DV0EN

DVOCK

Read/Write

RRRRR

R/W

After reset

00000

000

DVOEN

Enables/disables

the divider output

0: Disable the divider output

1: Enable the divider output

DVOCK

Selects the divider output frequency

Unit: [Hz]

NORMAL 1/2, IDLE 1/2 mode

SLOW1/2

SLEEP1

mode

DV9CK=0

DV9CK=1

fcgck/212

fs/25

fcgck/211

fs/24

fcgck/210

fs/23

fcgck/29

Reserved

DVOCR

Selector

DVOEN

DVO pin

DVOCK

fcgck/212 or fs/25

fcgck/211 or fs/24

fcgck/210 or fs/23

fcgck/29

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