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TMP89FS60 Datasheet(PDF) 151 Page - Toshiba Semiconductor

Part # TMP89FS60
Description  8 Bit Microcontroller
PDF  410 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP89FS60 Datasheet(HTML) 151 Page - Toshiba Semiconductor

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Page 137
TMP89FS60
RA001
12. Time Base Timer (TBT)
The time base timer generates the time base for key scanning, dynamic display and other processes. It also pro-
vides a time base timer interrupt (INTTBT) in a certain cycle.
12.1 Time Base Timer
12.1.1 Configuration
Figure 12-1 Time Base Timer Configuration
12.1.2 Control
The time base timer is controlled by the time base timer control register (TBTCR).
Note 1: fcgck : Gear clock [Hz], fs : Low-frequency clock [Hz]
Note 2: When the operation is changed to the STOP mode, TBTCR<TBTEN> is cleared to "0" and TBTCR<TBTCK> maintains
the value.
Time base timer control register
TBTCR
(0x0039)
76543
210
Bit Symbol
----
TBTEN
TBTCK
Read/Write
RRRR
R/W
R/W
After reset
00000
000
TBTEN
Enables/disables the time base
timer interrupt requests
0: Disables generation of interrupt request signals
1: Enables generation of interrupt request signals
TBTCK
Selects the time base timer interrupt
frequency
Unit: [Hz]
TBTCK
NORMAL 1/2, IDLE 1/2 mode
SLOW1/2, SLEEP1
mode
DV9CK = 0
DV9CK = 1
000
fcgck/222
fs/215
fs/215
001
fcgck/220
fs/213
fs/213
010
fcgck/215
fs/28
Reserved
011
fcgck/213
fs/26
Reserved
100
fcgck/212
fs/25
Reserved
101
fcgck/211
fs/24
Reserved
110
fcgck/210
fs/23
Reserved
111
fcgck/28
Reserved
Reserved
Falling edge
detector
TBTCR
Source clock
TBTEN
TBTCK
3
INTTBT
Interrupt request
IDLE0, SLEEP0
Release request
fcgck/222 or fs/215
fcgck/220 or fs/213
fcgck/215 or fs/28
fcgck/213 or fs/26
fcgck/212 or fs/25
fcgck/211 or fs/24
fcgck/210 or fs/23
fcgck/28



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