TMP89FS60 datasheet(148/410 Pages) TOSHIBA

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Page 134

11. Divider Output (DVO)

11.2 Control

TMP89FS60

RA001

The divider output is enabled by setting DVOCR<DVOEN> to "1". Then, The rectangular waves selected by

DVOCR<DVOCK> is output from DVO pin.

It is disabled by clearing DVOVR<DVOEN> to "0". And DVO pin keeps "H" level.

When the operation is changed to STOP or IDLE0/SLEEP0 mode, DVOCR<DVOEN> is cleared to "0" and

the DVO pin outputs the "H" level.

The divider output source clock operates, regardless of the value of DVOCR<DVOEN>.

Therefore, the frequency of the first divider output after DVOCR<DVOEN> is set to "1" is not the frequency

set at DVOCR<DVOCK>.

When the operation is changed to the software, STOP or IDLE0/SLEEP0 mode is activated and

DVOCR<DVOEN> is cleared to "0", the frequency of the divider output is not the frequency set at

DVOCR<DVOCK>.

Figure 11-2 Divider Output Timing

When the operation is changed from NORMAL mode to SLOW mode or from SLOW mode to NORMAL

mode, the divider output frequency does not reach the expected value due to synchronization of the gear clock

(fcgck) and the low-frequency clock (fs).

Example: 1.953 kHz pulse output (fcgck = 8.0 MHz)

(DVOCR), 00000100B

; DVOCK

← "00", DVOEN ← "1"

Table 11-1 Divider Output Frequency (Example: fcgck = 8.0 MHz, fs = 32.768 kHz)

DVOCK

Divider output frequency [Hz]

NORMAL 1/2, IDLE 1/2 mode

SLOW1/2, SLEEP1

mode

DV9CK = 0

DV9CK = 1

1.953 k

1.024 k

3.906 k

2.048 k

7.813 k

4.096 k

15.625 k

Reserved

TBTCR<DVOEN>

Divider output timing chart

DVO output

TMP89FS60 Datasheet(PDF) 148 Page - Toshiba Semiconductor

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