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TMP89FS60 Datasheet(PDF) 160 Page - Toshiba Semiconductor |
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TMP89FS60 Datasheet(HTML) 160 Page - Toshiba Semiconductor |
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160 / 410 page ![]() Page 146 13. 16-bit Timer Counter (TCA) 13.2 Control TMP89FS60 RA001 Note 1: TA0OVF, TA0CPFA and TA0CPFB are cleared to "0" automatically after TA0SR is read. Writing to TA0SR is invalid. Note 2: When a read instruction is executed on TA0SR, bits 6 to 2 are read as "0". Note 1: When a write instruction is executed on TA0DRAL (TA0DRBL), the set value does not become effective immedi- ately, but is temporarily stored in the temporary buffer. Subsequently, when a write instruction is executed on the higher-level register, TA0DRAH (TA0DRBH), the 16-bit set values are collectively stored in the double buffer or TA0DRAL/H. When setting data to the timer counter A0 register, be sure to write the data into the lower level reg- ister and the higher level in this order. Note 2: The timer counter A0 register is not writable in the pulse width measurement mode. Timer counter A0 status register TA0SR 76543 210 (0x0033) Bit Symbol TA0OVF ---- - TA0CPFA TA0CPFB Read/Write RRRRRRRR After reset 00000 000 TA0OVF Overflow flag 0 1 No overflow has occurred. At least an overflow has occurred. TA0CPFA Capture completion flag A 0 1 No capture operation has been executed. At least a pulse width capture has been executed in the double-edge capture. TA0CPFB Capture completion flag B 0 1 No capture operation has been executed. At least a capture operation has been executed in the single-edge cap- ture. At least a pulse duty width capture has been executed in the double- edge capture. Timer counter A0 register AH TA0DRAH 15 141312 11 10 9 8 (0x002E) Bit Symbol TA0DRAH Read/Write R/W After reset 11111 111 Timer counter A0 register AL TA0DRAL 76543 210 (0x002D) Bit Symbol TA0DRAL Read/Write R/W After reset 11111 111 Timer counter A0 register BH TA0DRBH 15 141312 11 10 9 8 (0x0030) Bit Symbol TA0DRBH Read/Write R/W After reset 11111 111 Timer counter A0 register BL TA0DRBL 76543 210 (0x002F) Bit Symbol TA0DRBL Read/Write R/W After reset 11111 111 |
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