TMP89FS60 datasheet(162/410 Pages) TOSHIBA

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Page 148

13. 16-bit Timer Counter (TCA)

13.4 Timer Function

TMP89FS60

RA001

13.4 Timer Function

Timer counter A0 has six types of operation modes; timer, external trigger timer, event counter, window, pulse

width measurement and programmable pulse generate (PPG) output modes.

13.4.1 Timer mode

In the timer mode, the up-counter counts up using the internal clock, and interrupts can be generated regu-

larly at specified times.

13.4.1.1 Setting

Setting the operation mode selection TA0MOD<TA0M> to "000" or "001" activates the timer mode.

Select the source clock at TA0MOD<TA0CK>.

Setting TA0CR<TA0S> to "1" starts the timer operation. After the timer is started, writing to TA0MOD

and TA0CR<TA0OVE> becomes invalid. Be sure to complete the required mode settings before starting

the timer.

13.4.1.2 Operation

Setting TA0CR<TA0S> to "1" allows the 16-bit up counter to increment based on the selected internal

source clock. When a match between the up-counter value and the value set to timer register A

(TA0DRA) is detected, an INTTA0 interrupt request is generated and the up counter is cleared to

"0000H". After being cleared, the up counter continues counting. Setting TA0CR<TA0S> to "0" during

the timer operation causes the up counter to stop counting and be cleared to "0000H".

13.4.1.3 Auto capture

The latest contents of the up counter can be taken into timer register B (TA0DRB) by setting

TA0CR<TA0ACAP> to "1" (auto capture function). When TA0CR<TA0ACAP> is "1", the current con-

tents of the up counter can be read by reading TA0DRBL. TA0DRBH is loaded at the same time as

TA0DRBL is read. Therefore, when reading the captured value, be sure to read TA0DRBL and

TA0DRBH in this order. (The capture time is the timing when TA0DRBL is read.) The auto capture func-

tion can be used whether the timer is operating or stopped. When the timer is stopped, TA0DRBL is read

as "00H". TA0DRBH keeps the captured value after the timer stops, but it is cleared to "00H" when

TA0DRBL is read while the timer is stopped.

If the timer is started with TA0CR<TA0ACAP> written to "1", the auto capture is enabled immediately

after the timer is started.

Note 1: The value set to TA0CR<TA0ACAP> cannot be changed at the same time as TA0CR<TA0S> is

rewritten from "1" to "0". (This setting is invalid.)

Table 13-3 Timer Mode Resolution and Maximum Time Setting

TA0MOD

<TA0CK>

Source clock [Hz]

Resolution

Maximum time setting

NORMAL 1/2 or IDLE 1/2 mode

SLOW1/2 or

SLEEP1 mode

fcgck=8MHz

fs=32.768KHz

fcgck=8MHz

fs=32.768KHz

SYSCR1<DV9CK>

= "0"

SYSCR1<DV9CK>

= "1"

fcgck/210

fs/23

128

µs

244.1us

8.4s

16s

fcgck/26

-8

µs

524.3ms

fcgck/22

500ns

32.8ms

fcgck/2

250ns

16.4ms

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