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TMP89FS60 Datasheet(PDF) 237 Page - Toshiba Semiconductor

Part # TMP89FS60
Description  8 Bit Microcontroller
PDF  410 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP89FS60 Datasheet(HTML) 237 Page - Toshiba Semiconductor

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Page 223
TMP89FS60
RA001
16.10Received Data Noise Rejection
When noise rejection is enabled at UART0CR2<RXDNC>, the time of pulses to be regarded as signals is as
shown in Table 16-8.
Note 1: The transfer base clock frequency is the clock frequency selected at UARTCR1<BRG>.
Figure 16-9 Received Data Noise Rejection
Table 16-8 Received Data Noise Rejection Time
RXDNC
Noise rejection time [s]
Time of pulses to be regarded as signals
00
No noise rejection
-
01
(UART0DR+1)/(Transfer base clock frequency)
2
× (UART0DR+1)/(Transfer base clock frequency)
10
2
× (UART0DR+1)/(Transfer base clock frequency)
4
× (UART0DR+1)/(Transfer base clock frequency)
11
4
× (UART0DR+1)/(Transfer base clock frequency)
8
× (UART0DR+1)/(Transfer base clock frequency)
Receiving continues
because the start bit is 0
The received data is taken into
the shift register
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0 15 14 13 12 11 10 9
8
7
6
5
4
3
Bit 0
Start bit
Start bit
Bit 0
RT clock
Internal received
data
Shift register
Bit 0
RXD0 pin
Noise
Noise is removed
A falling edge
is detected
When the noise rejection
circuit is used



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