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TMP89FS60 Datasheet(PDF) 233 Page - Toshiba Semiconductor

Part # TMP89FS60
Description  8 Bit Microcontroller
PDF  410 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP89FS60 Datasheet(HTML) 233 Page - Toshiba Semiconductor

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Page 219
TMP89FS60
RA001
Figure 16-4 Fine Adjustment of Baud Rate Clock Using UART0CR2<RTSEL>
16.8.1.2 Calculation of set values of UART0CR2<RTSEL> and UART0DR
The set value of UART0DR for an operating frequency and baud rate can be calculated using the calcu-
lation formula shown in Figure 16-5. For example, to generate a basic baud rate of 38400 [baud] with
fcgck=4 [MHz], calculate the set value of UART0DR for each setting of UART0CR2<RTSEL> and com-
pensate the calculated value to a positive number to obtain the generated baud rate as shown in Figure 16-
6. Basically, select the set value of UART0CR2<RTSEL> that has the smallest baud rate error from
among the generated baud rates. In Figure 16-6, the setting of UART0CR2<RTSEL>="0y010" has the
smallest error among the calculated baud rates, and thus the generated baud rate is 38095 [baud] (
−0.79%)
against the basic baud rate of 38400 [baud].
Note: The error from the basic baud rate should be accurate to within
±3%. Even if the error is within ±3%, the
communication may fail due to factors such as frequency errors of external controllers (for example, a
personal computer) and oscillators and the load capacity of the communication pin.
Figure 16-5 UART0DR Calculation Method (When BRG Is Set to fcgck)
Start
123456789
10
11
12
Bit 0
Stop 1
Start
Bit 0
Stop 1 Stop 2
Stop 1
Stop 1 Stop 2
Start
Bit 0
Bit 0
Start
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 Parity
Parity
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
0
1
0
1
0
0
1
1
STBT
PE
000
001
010
011
100
16
16
15
15
17
16
17
15
16
17
16
16
15
15
17
16
17
15
16
17
16
16
15
15
17
16
17
15
16
17
16
16
15
15
17
16
17
15
16
17
16
16
15
15
17
16
17
15
16
17
16
16
15
15
17
16
fcgck
[baud]
16
(UARTDR+1)
Generated baud rate
*When BRG is set to fcgck
17
15
16
17
RTSEL
Transfer frame
fcgck
[baud]
16.5
(UARTDR+1)
fcgck
[baud]
15
(UARTDR+1)
fcgck
[baud]
15.5
(UARTDR+1)
fcgck
[baud]
17
(UARTDR+1)
Number of RT clocks
000
fcgck [Hz]
1
1
1
1
1
UARTDR =
16
A [baud]
UARTDR set value
RTSEL
001
fcgck [Hz]
UARTDR =
16.5
A [baud]
010
fcgck [Hz]
UARTDR =
15
A [baud]
011
fcgck [Hz]
UARTDR =
15.5
A [baud]
100
fcgck [Hz]
UARTDR =
17
A [baud]



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