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TMP89FS60 Datasheet(PDF) 232 Page - Toshiba Semiconductor |
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TMP89FS60 Datasheet(HTML) 232 Page - Toshiba Semiconductor |
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232 / 410 page ![]() Page 218 16. Asynchronous Serial Interface (UART) 16.8 Transfer Baud Rate TMP89FS60 RA001 Note 1: The overall error from the basic baud rate must be within ±3%. Even if the overall error is within ±3%, the commu- nication may fail due to factors such as frequency errors in external controllers (for example, a personal computer) and oscillators and the load capacity of the communication pin. 16.8.1 Transfer baud rate calculation method 16.8.1.1 Bit width adjustment using UART0CR2<RTSEL> The bit width of transmitted/received data can be finely adjusted by changing UART0CR2<RTSEL>. The number of RT clocks per bit can be changed in a range of 15 to 17 clocks by changing UART0CR2<RTSEL>. The RT clock is the transfer base clock, which is the pulses obtained by counting the clock selected at UART0CR1<BRG> the number of times of (UART0DR set value) + 1. Especially, when UART0CR2<RTSEL> is set to "0y001" or "0y011", two types of RT clocks alternate at each bit, so that the pseudo baud rates of RT × 15.5 clocks and RT × 16.5 clocks can be generated. The number of RT clocks per bit of transfer frame is shown in Figure 16-4. For example, when fcgck is 4 [MHz], UART0CR2<RTSEL> is set to "0y000" and UART0DR is set to "0x19", the baud rate calculated using the formula in Figure 16-4 is expressed as: fcgck / (16 × (UART0DR + 1) = 9615 [baud] These settings generate a baud rate close to 9600 [baud] (+0.16%). Table 16-7 Set Values of UART0DR and UART0CR2<RTSEL> for Transfer Baud Rates (fs=32.768 kHz, UART0CR2<RXDNC>=0y00) Basic baud rate [baud] Register Operating frequency 32.768 kHz 300 UART0DR 0x06 RTSEL 0y011 Error (+0.67%) 150 UART0DR 0x0D RTSEL 0y011 Error (+0.67%) 134 UART0DR 0x0E RTSEL 0y001 Error (-1.20%) 110 UART0DR 0x11 RTSEL 0y001 Error (+0.30%) 75 UART0DR 0x1C RTSEL 0y010 Error (+0.44%) |
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