TMP89FS60 datasheet(228/410 Pages) TOSHIBA

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Page 214

16. Asynchronous Serial Interface (UART)

16.4 Protection to Prevent UART0CR1 and UART0CR2 Regis-

ters from Being Changed

TMP89FS60

RA001

16.4 Protection to Prevent UART0CR1 and UART0CR2 Registers from Being

Changed

The TMP89FS60 has a function that protects the registers from being changed so that the UART communication

settings (for example, stop bit and parity) are not changed accidentally during the UART operation.

Specific bits of UART0CR1 and UART0CR2 can be changed only under the conditions shown in Table 16-3. If a

write instruction is executed on the register when it is protected from being changed, the bits remain unchanged and

keep their previous values.

Table 16-3 Changing of UART0CR1 and UART0CR2

Bit to be changed

Function

Conditions that allow the bit to be changed

UART0CR1

<TXE>

UART0SR

<TBSY>

UART0CR1

<RXE>

UART0SR

<RBSY>

UART0CR1<STOPBT>

Transmit stop bit length

Both of these bits are "0"

UART0CR1<EVEN>

Parity selection

All of these bits are "0"

UART0CR1<PE>

Parity addition

UART0CR1<IRDASEL>

TXD pin output selection

Both of these bits are "0"

UART0CR1<BRG>

Transfer base clock selec-

tion

All of these bits are "0"

UART0CR2<RTSEL>

Selection of number of RT

clocks

UART0CR2<RXDNC>

Selection of RXD pin input

noise rejection time

Both of these bits are "0"

UART0CR2<STOPBR>

Receive stop bit length

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