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TMP89FS60 Datasheet(PDF) 229 Page - Toshiba Semiconductor |
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TMP89FS60 Datasheet(HTML) 229 Page - Toshiba Semiconductor |
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229 / 410 page ![]() Page 215 TMP89FS60 RA001 16.5 Activation of STOP, IDLE0 or SLEEP0 Mode 16.5.1 Transition of register status When the STOP, IDLE0 or SLEEP0 mode is activated, the UART stops automatically and each register becomes the status as shown in Table 16-4. For the registers that do not hold their values, make settings again as needed after the operation mode is recovered. 16.5.2 Transition of TXD pin status When the IDLE0, SLEEP0 or STOP mode is activated, the TXD pin reverts to the status shown in Table 16- 5, whether data is transmitted/received or the operation is stopped. Table 16-4 Transition of Register Status 7654321 0 UART0CR1 TXE RXE STOPBT EVEN PE IRDASEL BRG - Cleared to 0 Cleared to 0 Hold the value Hold the value Hold the value Hold the value Hold the value - UART0CR2 - - RTSEL RXDNC STOPBR -- Hold the value Hold the value Hold the value Hold the value Hold the value Hold the value UART0SR PERR FERR OERR - RBSY RBFL TBSY TBFL Cleared to 0 Cleared to 0 Cleared to 0 - Cleared to 0 Cleared to 0 Cleared to 0 Cleared to 0 UART0DR UART0DR7 UART0DR6 UART0DR5 UART0DR4 UART0DR3 UART0DR2 UART0DR1 UART0DR0 Hold the value Hold the value Hold the value Hold the value Hold the value Hold the value Hold the value Hold the value RD0BUF RD0DR7 RD0DR6 RD0DR5 RD0DR4 RD0DR3 RD0DR2 RD0DR1 RD0DR0 Indetermi- nate Indetermi- nate Indetermi- nate Indetermi- nate Indetermi- nate Indetermi- nate Indetermi- nate Indetermi- nate TD0BUF TD0DR7 TD0DR6 TD0DR5 TD0DR4 TD0DR3 TD0DR2 TD0DR1 TD0DR0 Indetermi- nate Indetermi- nate Indetermi- nate Indetermi- nate Indetermi- nate Indetermi- nate Indetermi- nate Indetermi- nate Table 16-5 TXD Pin Status When the STOP, IDLE0 or SLEEP0 Mode Is Activated UART0CR1 <IRDASEL> IDLE0 or SLEEP0 mode STOP mode SYSCR1<OUTEN>="1" SYSCR1<OUTEN>="0" "0" H level H level Hi-Z "1" L level L level |
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