TMP89FS60 datasheet(225/410 Pages) TOSHIBA

225 / 410 page

Page 211

TMP89FS60

RA001

Note 1: When a read instruction is executed on UART0CR2, bits 7 and 6 are read as "0".

Note 2: RTSEL can be set to two kinds of RT clocks for the even- and odd-numbered bits of the transfer frame. For details, refer to

"16.8.1 Transfer baud rate calculation method".

Note 3: For details of the RXDNC noise rejection time, refer to "16.10 Received Data Noise Rejection".

Note 4: When the STOP, IDLE0 or SLEEP0 mode is activated, the UART stops automatically but each bit value of UART0CR2

remains unchanged.

Note 5: When STOPBR is set to 2 bits, the first bit of the stop bits (during data receiving) is not checked for a framing error.

Note 6: To prevent RTSEL, RXDNC and STOPBR from being changed accidentally during the UART communication, the register

cannot be rewritten during the UART operation. For details, refer to "16.4 Protection to Prevent UART0CR1 and

UART0CR2 Registers from Being Changed".

Note 1: Set UART0CR1<RXE> and UART0CR1<TXE> to "0" before changing UART0DR. For the set values, refer to "16.8 Trans-

fer Baud Rate".

Note 2: When UART0CR1<BRG> is set to the TCA0 output, the value set to UART0DR has no meaning.

Note 3: When the STOP, IDLE0 or SLEEP0 mode is activated, the UART stops automatically but each bit value of UART0DR

remains unchanged.

UART0 control register 2

UART0CR2

76543210

(0x001B)

Bit Symbol

RTSEL

RXDNC

STOPBR

Read/Write

R/W

After reset

00000000

RTSEL

Selects the number of RT clocks

Odd-numbered bits

of transfer frame

Even-numbered bits

of transfer frame

000:

16 clocks

001:

16 clocks

17 clocks

010:

15 clocks

011:

15 clocks

16 clocks

100:

17 clocks

101:

Reserved

11*:

Reserved

RXDNC

Selects the RXD input noise rejec-

tion time

(Time of pulses to be removed as

noise)

00:

01:

10:

11:

No noise rejection

1 x (UART0DR+1)/(Transfer base clock frequency) [s]

2 x (UART0DR+1)/(Transfer base clock frequency) [s]

4 x (UART0DR+1)/(Transfer base clock frequency) [s]

STOPBR

Receive stop bit length

1 bit

2 bits

UART0 baud rate register

UART0DR

76543

210

(0x001C)

Bit Symbol

UART0DR7

UART0DR6

UART0DR5

UART0DR4

UART0DR3

UART0DR2

UART0DR1

UART0DR0

Read/Write

R/W

After reset

00000

000

UART0 status register

UART0SR

76543

210

(0x001D)

Bit Symbol

PERR

FERR

OERR

RBSY

RBFL

TBSY

TBFL

Read/Write

RRRRRRRR

After reset

00000

000

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