TMP89FS60 datasheet(224/410 Pages) TOSHIBA

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Page 210

16. Asynchronous Serial Interface (UART)

16.2 Control

TMP89FS60

RA001

Note 1: fcgck, Gear clock; fs, Low-frequency clock

Note 2: If the TXE or RXE bit is set to "0" during the transmission or receiving of data, the operation is not disabled until the data

transfer is completed. At this time, the data stored in the transmit data buffer is discarded.

Note 3: EVEN, PE and BRG settings are common to transmission and receiving.

Note 4: Set RXE and TXE to "0" before changing BRG.

Note 5: When BRG is set to the TCA0 output, the RT clock becomes asynchronous and the start bit of the transmitted/received

data may get shorter by a maximum of (UART0DR+1)/(Transfer base clock frequency)[s].

If the pin is not used for the TCA0 output, control the TCA0 output by using the port function control register.

Note 6: To prevent STOPBT, EVEN, PE, IRDASEL and BRG from being changed accidentally during the UART communication,

the register cannot be rewritten during the UART operation. For details, refer to "16.4 Protection to Prevent UART0CR1

and UART0CR2 Registers from Being Changed".

Note 7: When the STOP, IDLE0 or SLEEP0 mode is activated, TXE and RXE are cleared to "0" and the UART stops. Other bits

keep their values.

UART0 control register 1

UART0CR1

76543210

(0x001A)

Bit Symbol

TXE

RXE

STOPBT

EVEN

IRDASEL

BRG

Read/Write

R/W

After reset

00000000

TXE

Transmit operation

Disable

Enable

RXE

Receive operation

Disable

Enable

STOPBT

Transmit stop bit length

1 bit

2 bits

EVEN

Parity selection

Odd-numbered parity

Even-numbered parity

Parity addition

No parity

Parity added

IRDASEL

TXD pin output selection

UART output

IrDA output

BRG

Transfer base clock selection

When SYSCR2<SYSCK> is "0"

When SYSCR2<SYSCK> is "1"

fcgck

TCA0 output

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