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TMP89FS60 Datasheet(PDF) 299 Page - Toshiba Semiconductor |
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TMP89FS60 Datasheet(HTML) 299 Page - Toshiba Semiconductor |
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299 / 410 page ![]() Page 285 TMP89FS60 RA001 18.6 AC Specifications The AC specifications are as listed below. The operating mode (fast or standard) mode should be selected suitable for frequency of fcgck. For these operating mode, refer to the following table. Note: For m and n, refer to"18.4.4.1 Clock source". Figure 18-23 Definition of Timing (No. 1) Table 18-6 AC Specifications (Circuit Output Timing) Parameter Symbol Standard mode Fast mode Unit MIN. MAX. MIN. MAX. SCL clock frequency fSCL 0 fcgck / (m+n) 0 fcgck / (m+n) kHz Hold time (re)start condition. This period is followed by generation of the first clock pulse. tHD;STA m / fcgck - m / fcgck - µs Low-level period of SCL clock (output) tLOW n / fcgck - n / fcgck - µs High-level period of SCL clock (output) tHIGH m / fcgck - m / fcgck - µs Low-level period of SCL clock (input) tLOW 5 / fcgck - 5 / fcgck - µs High-level period of SCL clock (input) tHIGH 3 / fcgck - 3 / fcgck - µs Restart condition setup time tSU;STA Depends on the software - Depends on the software - µs Data hold time tHD;DAT 0 5 / fcgck 0 5 / fcgck µs Data setup time tSU;DAT 250 - 100 - ns Rising time of SDA and SCL signals tr - 1000 - 300 ns Falling time of SDA and SCL signals tf - 300 - 300 ns Stop condition setup time tSU;STO m / fcgck - m / fcgck - µs Bus free time between the stop condi- tion and the start condition tBUF Depends on the software - Depends on the software - µs Time before rising of SCL after SBICR2<PIN> is changed from "0" to "1" tSU;SCL n / fcgck - n / fcgck - µs t LOW t f t f t SU;STA t SU;STO t BUF t HD;STA t r t SU;DAT t HD;STA t HIGH t HD;DAT t f |
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