TMP89FS60 datasheet(295/410 Pages) TOSHIBA

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TMP89FS60

RA001

2. Clear SBI0CR1<ACK> to "0" and set SBI0CR1<BC> to "001".

3. To set SBI0CR2<PIN> to "1", write a dummy data (0x00) to SBI0DBR.

Transfer 1-bit data by setting SBI0CR1<PIN> to "1".

In this case, since the master device is a receiver, the SDA line on a bus keeps the high level. The

transmitter receives the high-level signal as a negative acknowledge signal. The receiver indicates to

the transmitter that data transfer is complete.

After 1-bit data is received and an interrupt request has occurred, generate the stop condition to ter-

minate data transfer.

Figure 18-20 Termination of Data Transfer in the Master Receiver Mode

18.5.3.2 When SBI0SR2<MST> is "0" (Slave mode)

In the slave mode, a serial bus interface circuit operates either in the normal slave mode or in the slave

mode after losing arbitration.

In the slave mode, the conditions of generating the serial bus interface interrupt request (INTSBI0) are

follows:

• At the end of the acknowledge signal when the received slave address matches the value set by the

I2C0AR<SA> with SBI0CR1<NOACK> set at "0"

• At the end of the acknowledge signal when a "GENERAL CALL" is received with

SBI0CR1<NOACK> set at "0"

• At the end of transferring or receiving after matching of slave address or receiving of "GENERAL

CALL"

The serial bus interface circuit changes to the slave mode if arbitration is lost in the master mode. And

an interrupt request occurs when the word data transfer terminates after losing arbitration. The generation

of the interrupt request and the behavior of SBI0CR2<PIN> after losing arbitration are shown in Table 18-

Negative

acknowledge signal

to the transmitter

2345678

SCL0 pin

SDA0 pin

SBI0CR<PIN>

INTSBI0 Interrupt

request

After reading the reveived

data, set SBI0CR1<BC> to

"001" and write dummy data

(0x00)

After reading the received data, clear

SBI0CR1<ACK> to "0" and writing the

dummy data (0x00)

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