TMP89FS60 datasheet(292/410 Pages) TOSHIBA

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18. Serial Bus Interface (SBI)

18.5 Data Transfer of I2C Bus

TMP89FS60

RA001

18.5 Data Transfer of I2C Bus

18.5.1 Device initialization

Set POFFCR1<SBI0EN> to "1".

After confirming that the serial bus interface pin is high level, set SBI0CR2<SBIM> to "1" to select the

serial bus interface mode.

Set SBI0CR1<ACK> to "1", SBI0CR1<NOACK> to "0" and SBI0CR1<BC> to "000" to count the number

of clocks for an acknowledge signal, to enable the slave address match detection and the GENERAL CALL

detection, and set the data length to 8 bits. Set THIGH and TLOW at SBI0CR1<SCK>.

Set a slave address at I2C0AR<SA> and set I2C0AR<ALS> to "0" to select the I2C bus mode.

Finally, set SBI0CR2<MST>, SBI0CR2<TRX> and SBI0CR2<BB> to "0", SBI0CR2<PIN> to "1" and

SBI0CR2<SWRST> to "00" for specifying the default setting to a slave receiver mode.

Note:The initialization of a serial bus interface circuit must be complete within the time from all devices which are

connected to a bus have initialized to and device does not generate a start condition. If not, the data can not

be received correctly because the other device starts transferring before an end of the initialization of a serial

bus interface circuit.

18.5.2 Start condition and slave address generation

Confirm a bus free status (SBI0SR2<BB>="0").

Set SBI0CR1<ACK> to "1" and specify a slave address and a direction bit to be transmitted to the

SBI0DBR.

By writing "1" to SBI0CR2<MST>, SBI0CR2<TRX>, SBI0CR2<BB> and SBI0CR2<PIN>, the start condi-

tion is generated on a bus and then, the slave address and the direction bit which are set to the SBI0DBR are

output. The time from generating the START condition until the falling SBI0 pin takes tHIGH.

An interrupt request occurs at the 9th falling edge of a SCL clock cycle, and SBI0CR2<PIN> is cleared to

"0". The SCL0 pin is pulled down to the low level while SBI0CR2<PIN> is "0". When an interrupt request

occurs, SBI0CR2<TRX> changes by the hardware according to the direction bit only when an acknowledge

signal is returned from the slave device.

Note 1: Do not write a slave address to the SBI0DBR while data is transferred. If data is written to the SBI0DBR,

data to be output may be destroyed.

Note 2: The bus free state must be confirmed by software within 98.0

µs (the shortest transmitting time according to

the standard mode I2C bus standard) or 23.7

µs (the shortest transmitting time according to the fast mode

I2C bus standard) after setting of the slave address to be output. Only when the bus free state is confirmed,

set "1" to SBI0CR2<MST>, SBI0CR2<TRX>, SBI0CR2<BB> and SBI0CR2<PIN> to generate the start

conditions. If the writing of slave address and setting of SBI0CR2<MST>, SBI0CR2<TRX>, SBI0CR2<BB>

and SBI0CR2<PIN> doesn't finish within 98.0

µs or 23.7µs, the other masters may start the transferring and

the slave address data written in SBI0DBR may be broken.

Example :Initialize a device

CHK_PORT:

CMP

(P2PRD), 0x0C

; Checks whether the serial bus interface pin is at the high level

NZ, CHK_PORT

(SBI0CR2), 0x18

; Selects the serial bus interface mode

(SBI0CR1), 0x16

; Selects the acknowledgment mode and sets SBI0CR1<SCK> to

"110"

(I2C0AR), 0xa0

; Sets the slave address to 1010000 and selects the I2C bus mode

(SBI0CR2), 0x18

; Selects the slave receiver mode

TMP89FS60 Datasheet(PDF) 292 Page - Toshiba Semiconductor

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