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TMP89FS60 Datasheet(PDF) 290 Page - Toshiba Semiconductor

Part # TMP89FS60
Description  8 Bit Microcontroller
PDF  410 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP89FS60 Datasheet(HTML) 290 Page - Toshiba Semiconductor

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Page 276
18. Serial Bus Interface (SBI)
18.4 Functions
TMP89FS60
RA001
Figure 18-13 Example When Master B is a Serial Bus Interface Circuit
18.4.12Slave address match detection monitor
In the slave mode, SBI0SR2<AAS> is set to "1" when the received data is "GENERAL CALL" or the
received data matches the slave address setting by I2C0AR<SA> with SBI0CR1<NOACK> set at "0" and the
I2C bus mode is active (I2C0AR<ALS>="0").
Setting SBI0CR1<NOACK> to "1" disables the subsequent slave address match and GENERAL CALL
detections. SBI0SR2<AAS> remains at "0" even if a "GENERAL CALL" is received or the same slave
address as the I2C0AR<SA> set value is received.
When a serial bus interface circuit operates in the free data format (I2C0AR<ALS>= "1"), SBI0SR2<AAS>
is set to "1" after receiving the first 1-word of data. SBI0SR2<AAS> is cleared to "0" by writing data to the
SBI0DBR or reading data from the SBI0DBR.
Figure 18-14 Changes in the Slave Address Match Detection Monitor
SCL pin
SDA pin
SCL pin
SDA pin
D4A
123
123
456789
12
3456789
Master A
Master B
Stop clock output
Releasing SDA pin and SCL pin
to high level as losing arbitration.
D5A
D6A
D7A
D3A D2A D1A D0A
D6A
D7A
D5A’
D6A’
D7A’
SBI0SR2<AL>
SBI0CR2<MST>
SBI0CR2<PIN>
INTSBI0 Interrupt request
Access to SBI0DBR or
SBI0CR2
Start condition
Output of an acknowledge signal
Slave address + Direction bit
SA6
SA5
SA4
SA3
SA2
SA1
SA0
R/W
SCL0 (Bus)
SDA0 (Bus)
SDA0 pin
INTSBI0 Interrupt request
Writing or reading SBI0DBR



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