TMP89FS60 datasheet(291/410 Pages) TOSHIBA

291 / 410 page

Page 277

TMP89FS60

RA001

18.4.13GENERAL CALL detection monitor

SBI0SR2<AD0> is set to "1" when SBI0CR1<NOACK> is "0" and GENERAL CALL (all 8-bit received

data is "0" immediately after a start condition) in a slave mode.

Setting SBI0CR1<NOACK> to "1" disables the subsequent slave address match and GENERAL CALL

detections. SBI0SR2<AD0> remains at "0" even if a "GENERAL CALL" is received.

SBI0SR2<AD0> is cleared to "0" when a start or stop condition is detected on a bus.

Figure 18-15 Changes in the GENERAL CALL Detection Monitor

18.4.14Last received bit monitor

The SDA line value stored at the rising edge of the SCL line is set to SBI0SR2<LRB>.

In the acknowledge mode, immediately after an interrupt request is generated, an acknowledge signal is read

by reading the contents of SBI0SR2<LRB>.

Figure 18-16 Changes in the Last Received Bit Monitor

18.4.15Slave address and address recognition mode specification

When the serial bus interface circuit is used in the I2C bus mode, clear I2C0AR<ALS> to "0", and set

I2C0AR<SA> to the slave address.

When the serial bus interface circuit is used with a free data format not to recognize the slave address, set

I2C0AR<ALS> to "1". With a free data format, the slave address and the direction bit are not recognized, and

they are processed as data from immediately after the start condition.

Start condition

Stop condition

Output of an acknowledge signal

GENERAL CALL

23456789

SCL (Bus)

SDA (Bus)

SDA0 端子

SBI0SR2<AD0>

INTSBI0 Interrupt request

Acknowledgment

23456789

Acknowledgment

SCL

SDA

SBI0SR2<LRB>

TMP89FS60 Datasheet(PDF) 291 Page - Toshiba Semiconductor