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TMP89FS60 Datasheet(PDF) 287 Page - Toshiba Semiconductor |
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TMP89FS60 Datasheet(HTML) 287 Page - Toshiba Semiconductor |
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287 / 410 page ![]() Page 273 TMP89FS60 RA001 When the serial bus interface circuit operates in the free data format, a slave address and a direction bit are not recognized. They are handled as data just after generating the start condition. SBI0CR2<TRX> is not changed by the hardware. 18.4.7 Start/stop condition generation When SBI0SR2<BB> is "0", a slave address and a direction bit which are set to the SBI0DBR are output on a bus after generating a start condition by writing "1" to SBI0CR2 <MST>, SBI0CR2<TRX>, SBI0CR2<BB> and SBI0CR2<PIN>. It is necessary to set SBI0CR1<ACK> to "1" before generating the start condition. Figure 18-9 Generating the Start Condition and a Slave Address When SBI0CR2<BB> is "1", the sequence of generating the stop condition on the bus is started by writing "1" to SBI0CR2<MST>, SBI0CR2<TRX> and SBI0CR2<PIN> and writing "0" to SBI0CR2<BB>. When a stop condition is generated. The SCL line on a bus is pulled down to the low level by another device, a stop condition is generated after releasing the SCL line. Figure 18-10 Stop Condition Generation The bus condition can be indicated by reading the contents of SBI0SR2<BB>. SBI0SR2<BB> is set to "1" when the start condition on the bus is detected (Bus Busy State) and is cleared to "0" when the stop condition is detected (Bus Free State). Table 18-3 SBI0CR1<TRX> Operation in Each Mode Mode Direction bit Changing condition TRX after changing Slave mode "0" A received slave address is the same as the value set to I2C0AR<SA> "0" "1" "1" Master mode "0" ACK signal is returned "1" "1" "0" Slave address and direction bit Start condition Acknowledge signal 23456789 A3 A2 A1 A0 A4 A5 A6 R/W 1 SCL0 pin SDA0 pin INTSBI0 Interrupt request Stop condition SCL0 pin SDA0 pin |
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