TMP89FS60 datasheet(283/410 Pages) TOSHIBA

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TMP89FS60

RA001

Figure 18-5 Number of Clocks for Data Transfer and SBI0CR1<BC> and SBI0CR1<ACK>

The relationship between the number of clocks for data transfer and SBI0CR1<BC> and

SBI0CR1<ACK> is shown in Table 18-1.

BC is cleared to "000" by the start condition.

Therefore, the slave address and the direction bit are always transferred in 8-bit units. In other cases, BC

keeps the set value.

Note: SBI0CR1<ACK> must be set before transmitting or receiving a slave address. When SBI0CR1<ACK>

is cleared, the slave address match detection and the direction bit detection are not executed properly.

18.4.3.2 Output of an acknowledge signal

In the acknowledgment mode, the SDA0 pin changes as follows during the period of the clocks for an

acknowledge signal.

• In the master mode

In the transmitter mode, the SDA0 pin is released to receive an acknowledge signal from the

receiver during the period of the clocks for an acknowledge signal. In the receiver mode, the

SDA0 pin is pulled down to the low level and an acknowledge signal is generated during the

period of the clocks for an acknowledge signal.

• In the slave mode

When a match between the received slave address and the slave address set to I2C0AR<SA>

is detected or when a GENERAL CALL is received, the SDA0 pin is pulled down to the low

level and an acknowledge signal is generated during the period of the clocks for an acknowl-

edge signal.

Table 18-1 Relationship between the Number of Clocks for Data Transfer and SBI0CR1<BC>

and SBI0CR1<ACK>

ACK=0 (Non-acknowledgment mode)

ACK=1 (Acknowledgment mode)

Number of clocks for data

transfer

Number of data bits

Number of clocks for data

transfer

Number of data bits

000

001

010

011

100

101

110

111

SBI0CR1<BC>="110",

SBI0CR1<ACK>="0"

SBI0CR1<BC>="011",

SBI0CR1<ACK>="1"

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