TMP89FS60 datasheet(280/410 Pages) TOSHIBA

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Page 266

18. Serial Bus Interface (SBI)

18.3 Control

TMP89FS60

RA001

Note 1: When SBI0CR2<SBIM> is "0", no value can be written to SBI0CR2 except SBI0CR2<SBIM>. Before writing values to

SBI0CR2, write "1" to SBI0CR2<SBIM> to activate the serial bus interface mode.

Note 2: Don't change the contents of the registers, except SBI0CR2<SWRST>, when the start condition is generated, the stop

condition is generated or the data transfer is in progress. Write data to the registers before the start condition is generated

or during the period from when an interrupt request is generated for stopping the data transfer until it is released.

Note 3: Make sure that the port is in a high state before switching the port mode to the serial bus interface mode. Make sure that

the bus is free before switching the serial bus interface mode to the port mode.

Note 4: SBI0CR2 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit opera-

tion.

Note 5: After a software reset is generated, all the bits of SBI0CR2 register except SBI0CR2<SBIM> and the SBI0CR1, I2C0AR

and SBI0SR2 registers are initialized.

Note 6: When the operation is switched to STOP, IDLE0 or SLOW mode, the SBI0CR2 register, except SBI0CR2<SBIM>, and the

SBI0CR1, I2C0AR and SBI0DBR registers are initialized.

Note 1: * : Unstable

Note 2: When SBI0CR2<SBIM> becomes "0", SBI0SR is initialized.

Note 3: After a software reset is generated, all the bits of the SBI0CR2 register except SBI0CR2<SBIM> and the SBI0CR1,

I2C0AR and SBI0SR2 registers are initialized.

Note 4: When the operation is switched to STOP, IDLE0 or SLOW mode, the SBI0CR2 register, except SBI0CR2<SBIM>, and the

SBI0CR1, I2C0AR and SBI0DBR registers are initialized.

MST

Master/slave selection

0: Slave

1: Master

TRX

Transmitter/receiver selection

0: Receiver

1: Transmitter

Start/stop generation

0: Generate the stop condition (when MST, TRX and PIN are "1")

1: Generate the start condition (when MST, TRX and PIN are "1")

Cancel interrupt service request

0: - (Cannot clear this bit by the software)

1: Cancel interrupt service request

SBIM

Serial bus interface operation

mode register

0: Port mode

1: Serial bus interface mode

SWRST

Software reset start bit

The software reset starts by first writing "10" and next writing "01"

Serial bus interface status register 2

SBI0SR2

(0x0023)

76543

210

Bit Symbol

MST

TRX

AAS

AD0

LRB

Read/Write

RRRRRRRR

After reset

00010

MST

Master/slave selection status

monitor

0: Slave

1: Master

TRX

Transmitter/receiver selection

status monitor

0: Receiver

1: Transmitter

Bus status monitor

0: Bus free

1: Bus busy

Interrupt service requests sta-

tus monitor

0: Requesting interrupt service

1: Releasing interrupt service request

Arbitration lost detection monitor

0: -

1: Arbitration lost detected

AAS

Slave address match detection

monitor

0: -

1: Detect slave address match or "GENERAL CALL"

AD0

"GENERAL CALL" detection

monitor

0: -

1: Detect "GENERAL CALL"

LRB

Last received bit monitor

0: Last received bit is "0"

1: Last received bit is "1"

TMP89FS60 Datasheet(PDF) 280 Page - Toshiba Semiconductor

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