TMP89FS60 datasheet(279/410 Pages) TOSHIBA

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Page 265

TMP89FS60

RA001

Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock oscillation circuit clock

Note 2: Don't change the contents of the registers when the start condition is generated, the stop condition is generated or the

data transfer is in progress. Write data to the registers before the start condition is generated or during the period from

when an interrupt request is generated for stopping the data transfer until it is released.

Note 3: After a software reset is generated, all the bits of SBI0CR2 register except SBI0CR2<SBIM> and the SBI0CR1, I2C0AR

and SBI0SR2 registers are initialized.

Note 4: When the operation is switched to STOP, IDLE0 or SLOW mode, the SBI0CR2 register, except SBI0CR2<SBIM>, and the

SBI0CR1, I2C0AR and SBI0DBR registers are initialized.

Note 5: When fcgck is 4MHz, SCK should be not set to 0y000, 0y001 or 0y010 because it is not possible to satisfy the bus speci-

fication of fast mode.

Number of data bits

ACK=0

ACK=1

Number of

clocks for data

transfer

Number of data

bits

Number of clocks

for data transfer

Number of data bits

000:

001:

010:

011:

100:

101:

110:

111:

ACK

Generation and counting

of the clocks for an

acknowledge signal

ACK

Master mode

Slave mode

Not generating the clocks for an

acknowledge signal. Generate an

interrupt request when the data

transfer is finished

(non-acknowledgement mode)

Generate an interrupt request when the

data transfer is finished

(non-acknowledgement mode)

Generate the clocks for an

acknowledge signal and an inter-

rupt request when the data trans-

fer is finished

(acknowledgement mode)

Count the clocks for an acknowledge signal

and generate an interrupt request when the

data transfer is finished

(acknowledgement mode)

NOACK

Enables/disables the

slave address match

detection and the GEN-

ERAL CALL detection

NOACK

Master mode

Slave mode

Don’t Care

Enable the slave address match detection

and the GENERAL CALL detection

Don’t Care

Disable the slave address match detection

and the GENERAL CALL detection

SCK

HIGH and LOW periods

of the serial clock in the

master mode

Time before the release

of the SCL pin in the

slave mode

SCK

tHIGH(m/fcgck)

tLOW(n/fcgck)

fscl@fcgck=

8MHz

fscl@fcgck=

4MHz

000:

381KHz

Reserved (Note5)

001:

320KHz

Reserved (Note5)

010:

242KHz

Reserved (Note5)

011:

163KHz

82KHz

100:

99KHz

49KHz

101:

55KHz

28KHz

110:

135

138

29KHz

15KHz

111:

263

266

15KHz

8KHz

Serial bus interface control register 2

SBI0CR2

(0x0023)

76543

210

Bit Symbol

MST

TRX

SBIM

SWRST

Read/Write

WWWWW

After reset

00010

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