TMP89FS60 datasheet(284/410 Pages) TOSHIBA

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Page 270

18. Serial Bus Interface (SBI)

18.4 Functions

TMP89FS60

RA001

During the data transfer after the slave address match is detected or a "GENERAL CALL" is

received in the transmitter mode, the SDA0 pin is released to receive an acknowledge signal

from the receiver during the period of the clocks for an acknowledge signal.

In the receiver mode, the SDA0 pin is pulled down to the low level and an acknowledge sig-

nal is generated. Table 18-2 shows the states of the SCL0 and SDA0 pins in the acknowledg-

ment mode.

Note: In the non-acknowledgment mode, the clocks for an acknowledge signal are not generated or counted,

and thus no acknowledge signal is output.

18.4.4 Serial clock

18.4.4.1 Clock source

SBI0CR1<SCK> is used to set the HIGH and LOW periods of the serial clock to be output in the master

mode.

Table 18-2 States of the SCL0 and SDA0 Pins in the Acknowledgment Mode

Mode

Condition

Transmitter

Receiver

Master

SCL0

Add the clocks for an

acknowledge signal.

Add the clocks for an acknowl-

edge signal

SDA0

Release the pin to receive an

acknowledge signal

Output the low level as an

acknowledge signal to the pin

Slave

SCL0

Count the clocks for an

acknowledge signal

Count the clocks for an

acknowledge signal

SDA0

When the slave address

match is detected or a

"GENERAL CALL" is

received

Output the low level as an

acknowledge signal to the pin

During transfer after the

slave address match is

detected or a "GEN-

ERAL CALL" is received

Release the pin to receive an

acknowledge signal

Output the low level as an

acknowledge signal to the pin

SCK

tHIGH(m/fcgck)

tLOW(n/fcgck)

000:

001:

010:

011:

100:

101:

110:

135

138

111:

263

266

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