TMP89FS60 datasheet(285/410 Pages) TOSHIBA

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Page 271

TMP89FS60

RA001

Figure 18-6 SCL Output

Note: There are cases where the HIGH period differs from tHIGH selected at SBI0CR1<SCK> when the rising

edge of the SCL pin becomes blunt due to the load capacity of the bus.

In the master mode, the hold time when the start condition is generated is tHIGH [s] and the setup time

when the stop condition is generated is tHIGH [s].

When SBI0CR2<PIN> is set to "1" in the slave mode, the time that elapses before the release of the

SCL pin is tLOW [s].

In both the master and slave modes, the high level period must be 3/fcgck[s] or longer and the low level

period must be 5/fcgck[s] or longer for the externally input clock, regardless of the SBI0CR1<SCK> set-

ting.

Figure 18-7 SCL Input

18.4.4.2 Clock synchronization

In the I2C bus, due to the structure of the pin, in order to drive a bus with a wired AND, a master device

which pulls down a clock pulse to low will, in the first place, invalidate the clock pulse of another master

device which generates a high-level clock pulse. Therefore, the master outputting the high level must

detect this to correspond to it.

The serial bus interface circuit has a clock synchronization function. This function ensures normal

transfer even if there are two or more masters on the same bus.

The example explains clock synchronization procedures when two masters simultaneously exist on a

bus.

1/fscl

tLOW

tHIGH

= m / fcgck

= n / fcgck

HIGH

tLOW

fscl = 1/(tHIGH +

)

tLOW

SCL output

SCL input

HIGH

tLOW

tHIGH

TMP89FS60 Datasheet(PDF) 285 Page - Toshiba Semiconductor