TMP89FS60 datasheet(286/410 Pages) TOSHIBA

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18. Serial Bus Interface (SBI)

18.4 Functions

TMP89FS60

RA001

Figure 18-8 Example of Clock Synchronization

As Master 1 pulls down the SCL pin to the low level at point "a", the SCL line of the bus becomes the

low level. After detecting this situation, Master 2 resets counting a clock pulse in the high level and sets

the SCL pin to the low level.

Master 1 finishes counting a clock pulse in the low level at point "b" and sets the SCL pin to the high

level. Since Master 2 holds the SCL line of the bus at the low level, Master 1 waits for counting a clock

pulse in the high level. After Master 2 sets a clock pulse to the high level at point "c" and detects the SCL

line of the bus at the high level, Master 1 starts counting a clock pulse in the high level. Then, the master,

which has finished the counting a clock pulse in the high level, pulls down the SCL pin to the low level.

The clock pulse on the bus is determined by the master device with the shortest high-level period and

the master device with the longest low-level period from among those master devices connected to the

bus.

18.4.5 Master/slave selection

To set a master device, SBI0CR2<MST> should be set to "1".

To set a slave device, SBI0CR2<MST> should be cleared to "0". When a stop condition on the bus or an

arbitration lost is detected, SBI0CR2<MST> is cleared to "0" by the hardware.

18.4.6 Transmitter/receiver selection

To set the device as a transmitter, SBI0CR2<TRX> should be set to "1". To set the device as a receiver,

SBI0CR2<TRX> should be cleared to "0".

For the I2C bus data transfer in the slave mode, SBI0CR2<TRX> is set to "1" by the hardware if the direction

bit (R/W) sent from the master device is "1", and is cleared to "0" if the bit is "0".

In the master mode, after an acknowledge signal is returned from the slave device, SBI0CR2<TRX> is

cleared to "0" by hardware if a transmitted direction bit is "1", and is set to "1" by hardware if it is "0". When

an acknowledge signal is not returned, the current condition is maintained.

When a stop condition on the bus or an arbitration lost is detected, SBI0CR2<TRX> is cleared to "0" by the

hardware. Table 18-3 shows SBI0CR2<TRX> changing conditions in each mode and SBI0CR2<TRX> value

after changing.

Note:When SBI0CR1<NOACK> is "1", the slave address match detection and the GENERAL CALL detection are

disabled, and thus SBI0CR2<TRX> remains unchanged.

Count start

SCL pin (Master 1)

SCL pin (Master 2)

SCL (Bus)

Count reset

Wait

Count reset

TMP89FS60 Datasheet(PDF) 286 Page - Toshiba Semiconductor