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TMP89FS60 Datasheet(PDF) 289 Page - Toshiba Semiconductor |
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TMP89FS60 Datasheet(HTML) 289 Page - Toshiba Semiconductor |
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289 / 410 page ![]() Page 275 TMP89FS60 RA001 A software reset is generated by writing "10" and then "01" to SBI0CR2<SWRST>. After a software reset is generated, the serial bus interface circuit is initialized and all the bits of SBI0CR2 register, except SBI0CR2<SBIM> and the SBI0CR1, I2C0AR<SA> and SBI0SR2 registers, are initialized. 18.4.11Arbitration lost detection monitor Since more than one master device can exist simultaneously on a bus, a bus arbitration procedure is imple- mented in order to guarantee the contents of transferred data. Data on the SDA line is used for bus arbitration of the I2C bus. The following shows an example of a bus arbitration procedure when two master devices exist simulta- neously on a bus. Master 1 and Master 2 output the same data until point "a". After that, when Master 1 outputs "1" and Master 2 outputs "0", since the SDA line of a bus is wired AND, the SDA line is pulled down to the low level by Master 2. When the SCL line of a bus is pulled-up at point "b", the slave device reads data on the SDA line, that is data in Master 2. Data transmitted from Master 1 becomes invalid. The state in Master 1 is called "arbitration lost". A master device which loses arbitration releases the SDA pin and the SCL pin in order not to effect data transmitted from other masters with arbitration. When more than one master sends the same data at the first word, arbitration occurs continuously after the second word. Figure 18-12 Arbitration Lost The serial bus interface circuit compares levels of a SDA line of a bus with its SDA pin at the rising edge of the SCL line. If the levels are unmatched, arbitration is lost and SBI0SR2<AL> is set to "1". When SBI0SR2<AL> is set to "1", SBI0CR2<MST> and SBI0CR2<TRX> are cleared to "0" and the mode is switched to a slave receiver mode. Thus, the serial bus interface circuit stops output of clock pulses during data transfer after the SBI0SR2<AL> is set to "1". After the data transfer is completed, SBICR2<PIN> is cleared to "0" and the SCL pin is pulled down to the low level. SBI0SR2<AL> is cleared to "0" by writing data to the SBI0DBR, reading data from the SBI0DBR or writing data to the SBI0CR2. ab SCL (Bus) SDA pin (Master 1) SDA pin (Master 2) SDA (Bus) The SDA pin becomes "1" after losing arbitration. |
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