TMP89FS60 datasheet(293/410 Pages) TOSHIBA

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TMP89FS60

RA001

Figure 18-17 Generating the Start Condition and the Slave Address

18.5.3 1-word data transfer

Check SBI0SR2<MST> by the interrupt process after a 1-word data transfer is completed, and determine

whether the mode is a master or slave.

18.5.3.1 When SBI0SR2<MST> is "1" (Master mode)

Check SBI0SR2<TRX> and determine whether the mode is a transmitter or receiver.

(1)

When SBI0SR2<TRX> is "1" (Transmitter mode)

Check SBI0SR2<LRB>. When SBI0SR2<LRB> is "1", a receiver does not request data. Imple-

ment the process to generate a stop condition (described later) and terminate data transfer.

When SBI0SR2<LRB> is "0", the receiver requests subsequent data. When the data to be transmit-

ted subsequently is other than 8 bits, set SBI0CR1<BC> again, set SBI0CR1<ACK> to "1", and

write the transmitted data to SBI0DBR.

After writing the data, SBI0CR2<PIN> becomes "1", a serial clock pulse is generated for transfer-

ring the subsequent 1-word data from the SCL0 pin, and then the 1-word data is transmitted from the

SDA0 pin.

After the data is transmitted, an interrupt request occurs. SBI0CR2<PIN> become "0" and the

SCL0 pin is set to the low level. If the data to be transferred is more than one word in length, repeat

the procedure from the SBI0SR2<LRB> checking above.

Example :Generate the start condition

CHK_BB:

TEST

(SBI0SR2).BB

; Confirms that the bus is free

F, CHK_BB

(SBI0DBR), 0xcb

; The transmission slave address 0x65 and the direction bit "1"

(SBI0CR2), 0xf8

; Write "1" to SBI0CR2<MST>, <TRX>, <BB> and <PIN> to "1"

Start condition

Slave address + Direction bit

23456789

Acknowledgem

ent signal from

a slave

Interrupt request

signal

SBI0CR1<PIN>

SCL0 pin

SDA0 pin

SBI0CR2 <TRX> is cleared to "0" when

the direction bit is "1"and an

acknowledge signal is returned.

SBI0CR2<TRX>

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